MC9S12C128CFUE Freescale Semiconductor, MC9S12C128CFUE Datasheet - Page 222

• Manufacturer Part Number: MC9S12C128CFUE
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C128CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4000 B
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 61
• Number Of Timers: 1
• Operating Supply Voltage: - 0.3 V to + 6.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7 Debug Module (DBGV1) Block Description
7.4.3.2
A breakpoint request to the CPU can be created if BKCEN in DBGC2 is set. Breakpoints based on a
successful comparator C match can be accomplished regardless of the mode of operation for comparator
A or B, and do not affect the status of the ARM bit. TAGC in DBGC2 is used to select either tagged or
forced breakpoint requests for comparator C. Breakpoints based on comparator C are disabled in LOOP1
mode.
7.5
The DBG module is disabled after reset.
The DBG module cannot cause a MCU reset.
7.6
The DBG contains one interrupt source. If a breakpoint is requested and BDM in DBGC2 is cleared, an
SWI interrupt will be generated.
222
BEGIN
Resets
Interrupts
0
0
0
0
1
1
1
1
Breakpoint Based on Comparator C
Because breakpoints cannot be disabled when the DBG is armed, one must
be careful to avoid an “infinite breakpoint loop” when using tagged-type C
breakpoints while the DBG is armed. If BDM breakpoints are selected,
executing a TRACE1 instruction before the GO instruction is the
recommended way to avoid re-triggering a breakpoint if one does not wish
to de-arm the DBG. If SWI breakpoints are selected, disarming the DBG in
the SWI interrupt service routine is the recommended way to avoid re-
triggering a breakpoint.
TRGSEL
0
0
1
1
0
0
1
1
DBGBRK
MC9S12C-Family / MC9S12GC-Family
Table 7-26. Breakpoint Setup
0
1
0
1
0
1
0
1
Fill trace buffer until trigger address
(no CPU breakpoint — keep running)
Fill trace buffer until trigger address, then a forced breakpoint
request occurs
Fill trace buffer until trigger opcode is about to execute
(no CPU breakpoint — keep running)
Fill trace buffer until trigger opcode about to execute, then a
tagged breakpoint request occurs
Start trace buffer at trigger address
(no CPU breakpoint — keep running)
Start trace buffer at trigger address, a forced breakpoint
request occurs when trace buffer is full
Start trace buffer at trigger opcode
(no CPU breakpoint — keep running)
Start trace buffer at trigger opcode, a forced breakpoint request
occurs when trace buffer is full
Rev 01.24
NOTE
Type of Debug Run
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