MC9S12C128CFUE Freescale Semiconductor, MC9S12C128CFUE Datasheet - Page 211

• Manufacturer Part Number: MC9S12C128CFUE
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C128CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4000 B
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 61
• Number Of Timers: 1
• Operating Supply Voltage: - 0.3 V to + 6.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

7.3.2.11
7.3.2.12
Freescale Semiconductor
Module Base + 0x002D
Module Base + 0x002E
Starting address location affected by INITRG register setting.
EXTCMP
PAGSEL
Reset
Reset
Field
7:6
5:0
W
W
R
R
Bit 15
Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in
11.
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively.)
In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address
is in the FLASH/ROM memory space.
Comparator B Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in
Debug Comparator B Extended Register (DBGCBX)
Debug Comparator B Register (DBGCB)
15
0
0
7
Table 7-11
PAGSEL
Figure 7-19. Debug Comparator B Extended Register (DBGCBX)
Figure 7-20. Debug Comparator B Register High (DBGCBH)
along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Also see
Bit 14
14
0
0
6
Table 7-22. DBGCBX Field Descriptions
Bit 13
MC9S12C-Family / MC9S12GC-Family
13
0
0
5
Bit 12
Rev 01.24
12
0
0
4
Description
Bit 11
11
0
0
3
Chapter 7 Debug Module (DBGV1) Block Description
EXTCMP
Bit 10
10
0
0
2
Bit 9
0
0
1
9
Table
Bit 8
Table 7-
0
0
0
8
7-20.
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