MC9S12C128CFUE Freescale Semiconductor, MC9S12C128CFUE Datasheet - Page 311

IC MCU 128K FLASH 25MHZ 80-QFP

MC9S12C128CFUE

Manufacturer Part Number
MC9S12C128CFUE
Description
IC MCU 128K FLASH 25MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12C128CFUE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4000 B
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
61
Number Of Timers
1
Operating Supply Voltage
- 0.3 V to + 6.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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Module Base + 0x0018 (CANIDAR4)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
AC[7:0]
Figure 10-20. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Field
7:0
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
0x0019 (CANIDAR5)
0x001A (CANIDAR6)
0x001B (CANIDAR7)
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
AC7
AC7
AC7
AC7
0
0
0
0
7
7
7
7
Table 10-20. CANIDAR4–CANIDAR7 Register Field Descriptions
AC6
AC6
AC6
AC6
6
0
6
0
6
0
6
0
MC9S12C-Family / MC9S12GC-Family
AC5
AC5
AC5
AC5
0
0
0
0
5
5
5
5
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
Rev 01.24
AC4
AC4
AC4
AC4
4
0
4
0
4
0
4
0
Description
AC3
AC3
AC3
AC3
0
0
0
0
3
3
3
3
AC2
AC2
AC2
AC2
2
0
2
0
2
0
2
0
AC1
AC1
AC1
AC1
0
0
0
0
1
1
1
1
AC0
AC0
AC0
AC0
0
0
0
0
0
0
0
0
311

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