MC9S12C128CFUE Freescale Semiconductor, MC9S12C128CFUE Datasheet - Page 256

• Manufacturer Part Number: MC9S12C128CFUE
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C128CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4000 B
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 61
• Number Of Timers: 1
• Operating Supply Voltage: - 0.3 V to + 6.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.3.2.1
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop
divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency
by 2 x (SYNR+1). PLLCLK will not be below the minimum VCO frequency (f
Read: anytime
Write: anytime except if PLLSEL = 1
256
Module Base + 0x0000
Reset
ARMCOP
Register
0x000B
Name
W
R
CRG Synthesizer Register (SYNR)
0
0
7
If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2
Bus Clock must not exceed the maximum operating system frequency.
Write to this register initializes the lock detector bit and the track detector
bit.
W
R
= Unimplemented or Reserved
Bit 7
Bit 7
0
0
0
6
Figure 9-3. CRG Register Summary (continued)
Figure 9-4. CRG Synthesizer Register (SYNR)
= Unimplemented or Reserved
Bit 6
6
0
SYN5
MC9S12C-Family / MC9S12GC-Family
PLLCLK
0
5
Bit 5
=
5
0
2xOSCCLKx
SYNR
Rev 01.24
NOTE
NOTE
0
4
Bit 4
4
0
--------------------------------- -
(
(
REFDV
SYNR
SYN3
0
3
+
Bit 3
+
1
3
0
1
)
)
SYN2
0
2
Bit 2
2
0
SCM
).
Freescale Semiconductor
SYN1
Bit 1
0
1
1
0
Bit 0
Bit 0
SYN0
0
0
0