MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 173

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, set the bit to 1.
TOF — Timer Overflow Flag
13.4.10 Timer Input Capture/Output Compare Registers
Freescale Semiconductor
TOF is set when the 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared
automatically by a write to the TFLG2 register with bit 7 set. See the explanation of the TCRE control
bit in
PTN
cleared). Any access to TCNT will clear the TFLG2 register, if the TFFCA
bit in the TSCR register is set.
13.4.8 Timer Interrupt Mask
Address: $008F
Address: $0090–$0091
DETECTOR
Figure 13-21. Timer Input Capture/Output Compare Register 0 (TC0)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
EDGE
Bit 15
Bit 7
TOF
Bit 7
Bit 7
Bit 7
0
0
0
Figure 13-20. Main Timer Interrupt Flag 2 (TFLG2)
Figure 13-19. C3F–C0F Interrupt Flag Setting
COUNTER
DELAY
Bit 14
Bit 6
6
0
0
6
0
6
0
M68HC12B Family Data Sheet, Rev. 9.1
Registers.)
Bit 13
Bit 5
5
0
0
5
0
5
0
TCN INPUT CAPTURE
16-BIT MAIN TIMER
TCNH IC HOLDING
REGISTER
REGISTER
Bit 12
Bit 4
4
0
0
4
0
4
0
Bit 11
Bit 3
3
0
0
3
0
3
0
BUFEN • LATQ • TFMOD
Bit 10
Bit 2
2
0
0
2
0
2
0
Bit 9
Bit 1
1
0
0
1
0
1
0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
0
0
0
0
Timer Registers
SET CNF
INTERRUPT
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