MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 326

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications
19.16 Multiplexed Expansion Bus Timing
326
Num
1. V
2. All timings are calculated for normal port drives.
3. Crystal input is required to be within 45% to 55% duty.
4. Reduced drive must be off to meet these timings.
5. Unequalled loading of pins will affect relative timing numbers.
6. This characteristic is affected by clock stretch.
7. Without TAG enabled
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
—
1
2
3
5
7
8
9
Add N × t
DD
Frequency of operation (E-clock frequency)
Cycle timet
Pulse width, E lowPW
Pulse width, E high
Address delay timet
Address valid time to ECLK riset
Multiplexed address hold timet
Address hold to data valid
Data hold to high impedancet
Read data setup time
Read data hold time
Write data delay time
Write data hold time
Write data setup time
Read/write delay timet
Read/write valid time to E riset
Read/write hold time
Low strobe
Low strobe
Low strobe
Address access time
Access time from E rise
DBE delay from ECLK rise
DBE valid timet
DBE hold time from ECLK fall
= 5.0 Vdc ± 10%, V
cyc
where N = 0, 1, 2, or 3, depending on the number of clock stretches.
Use of the multiplexed expansion bus at 8 MHz is discouraged due to TAD
delay factors.
(7)
(7)
(7)
cyc
delay timet
valid time to E riset
hold time
= 1/f
DBE
Characteristic
o
(6)
AD
= PW
SS
(6)
PW
(6)
EL
RWD
= t
= 0 Vdc, T
t
t
(6)
DSW
ACCA
= t
LSD
EH
EH
cyc
t
(6)
cyc
= t
ACCE
= t
/4 + delay
− t
= t
= PW
DHZ
t
cyc
/2 + delay
= t
DBED
MAH
RWV
cyc
DBED
cyc
(1), (2), (3), (4), (5)
AV
/4 + delay
cyc
= PW
LSV
/2 + delay
A
= t
/4 + delay
EH
M68HC12B Family Data Sheet, Rev. 9.1
= t
= T
= PW
= PW
− t
= t
AD
= PW
cyc
− t
AD
cyc
EH
L
− 20
to T
/4 + delay
DDW
EL
EL
/4 + delay
− t
− t
EL
− t
− t
DSR
DSR
H
− t
, unless otherwise noted
AD
RWD
LSD
NOTE
Delay
−18
−4
−2
27
18
18
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
Symbol
PW
PW
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AHDS
t
t
t
ACCA
ACCE
DBED
t
DBEH
t
DDW
DHW
DSW
RWD
RWV
RWH
t
MAH
DHR
t
DHZ
DSR
DBE
t
LSD
LSV
LSH
cyc
AD
f
AV
o
EH
EL
–6.2
31.2
11.8
Min
125
5.8
3.8
3.8
dc
59
59
—
13
30
—
—
25
—
25
—
25
—
—
—
–3
0
8 MHz
Max
67.5
45.2
62.5
57.5
57.5
27.6
27.8
57.5
Freescale Semiconductor
8.0
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
500
246
248
107
103
103
115
94
20
25
20
83
20
20
–3
dc
—
—
—
—
—
—
—
—
0
2 MHz
Max
152
132
165
143
143
323
223
133
8.0
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns