MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 297

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.5.2 Firmware Command
The bits in the BDM instruction register have these meanings when a firmware command is executed.
H/F — Hardware/Firmware Flag
DATA — Data Flag
R/W — Read/Write Flag
TTAGO — Trace, Tag, Go Field
REGN — Register/Next Field
Freescale Semiconductor
Indicates which register is being affected by a command. In the case of a READ_NEXT or
WRITE_NEXT command, index register X is pre-incremented by two and the word pointed to by X is
then read or written.
0 = Firmware control logic
1 = Hardware control logic
0 = No data
1 = Data included in command
0 = Write
1 = Read
Address: $FF00
Reset:
Read:
Write:
Figure 18-5. BDM Instruction Register (INSTRUCTION)
Bit 7
H/F
0
TTAGO Value
TTAGO Value
DATA
6
0
M68HC12B Family Data Sheet, Rev. 9.1
000
001
010
011
00
01
10
11
Table 18-5. TTAGO Decoding
Table 18-6. REGN Decoding
R/W
5
0
4
0
TTAGO
READ/WRITE NEXT
3
0
Instruction
Instruction
TRACE1
TAGGO
GO
PC
—
—
—
2
0
Background Debug Mode (BDM)
REGN
1
0
Bit 0
0
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