MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 57

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Addr.
$011C
$011D
$013C
$013D
$011A
$011B
$011E
$011F
$0120
$013E
$013F
$0140
$014F
$0150
$015F
Notes:
↓
↓
↓
1. Available only on MC68HC912B32 and MC68HC912BC32 devices.
2. Available only on MC68HC912B32 and MC68HC12BE32 devices.
3. Available only on MC68HC(9)12BC32 devices.
msCAN12 Port CAN Data Direction
msCAN12 Port CAN Data Register
msCAN12 Identifier Acceptance
msCAN12 Identifier Acceptance
msCAN12 Port CAN Control
Register Name
msCAN12 Identifier Mask
msCAN12 Identifier Mask
msCAN12 Identifier Mask
msCAN12 Identifier Mask
Register 4 (CIDMR4)
Register 5 (CIDMR5)
Register 6 (CIDMR6)
Register 7 (CIDMR7)
Register (PCTLCAN)
Register 6 (CIDAR6)
Register 7 (CIDAR7)
Register (DDRCAN)
(PORTCAN)
See page 273.
See page 273.
See page 274.
See page 274.
See page 274.
See page 274.
See page 275.
See page 275.
See page 276.
Reserved
Reserved
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
Figure 2-1. Register Map (Sheet 18 of 19)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
M68HC12B Family Data Sheet, Rev. 9.1
DDRCAN7 DDRCAN6 DDRCAN5 DDRCAN4 DDRCAN3 DDRCAN2
PCAN7
Bit 7
AM7
AM7
AM7
AM7
AC7
AC7
R
R
0
0
0
= Unimplemented
PCAN6
AM6
AM6
AM6
AM6
AC6
AC6
TRANSMIT BUFFER 0 (Tx0)
RECEIVE BUFFER (RxFG)
R
R
6
0
0
0
PCAN5
AM5
AM5
AM5
AM5
AC5
AC5
R
R
5
0
0
0
PCAN4
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
AM4
AM4
AM4
AM4
AC4
AC4
R
R
R
4
0
0
0
(3)
(3)
— SEE
— SEE
= Reserved
PCAN2
AM3
AM3
AM3
AM3
AC3
AC3
R
R
3
0
0
0
16.3.2 Receive Structures
16.3.3 Transmit Structures
PCAN2
AM2
AM2
AM2
AM2
AC2
AC2
R
R
2
0
0
0
U = Unaffected
PUECAN
TxCAN
AM1
AM1
AM1
AM1
AC1
AC1
R
R
1
0
0
0
Registers
RDPCAN
RxCAN
Bit 0
AC0
AC0
AM0
AM0
AM0
AM0
R
R
0
0
0
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