MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 300

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Development Support
18.4.1 Breakpoint Modes
Three modes of operation determine the type of breakpoint in effect.
Breakpoints do not occur when BDM is active.
18.4.1.1 SWI Dual Address Mode
In this mode, dual address-only breakpoints can be set, each of which causes a software interrupt. This
is the only breakpoint mode which can force the CPU to execute an SWI. Program fetch tagging is the
default in this mode; data breakpoints are not possible. In dual mode each address breakpoint is affected
by the respective BKALE bit. The BKxRW, BKxRWE, BKMBH, and BKMBL bits are ignored. In dual
address mode, the BKDBE becomes an enable for the second address breakpoint.
18.4.1.2 BDM Full Breakpoint Mode
This is a single full-featured breakpoint which causes the part to enter background debug mode. BK1ALE,
BK1RW, and BK1RWE have no meaning in full breakpoint mode.
BKDBE enables data compare but has no meaning if BKPM = 1. BKMBH and BKMBL allow masking of
high and low byte compares but has no meaning if BKPM = 1. BK0ALE enables compare of low address
byte.
18.4.1.3 BDM Dual Address Mode
This mode has dual address-only breakpoints, each of which causes the part to enter background debug
mode. In dual mode, each address breakpoint is affected by the BKPM bit, the BKxALE bits, and the
BKxRW and BKxRWE bits. In dual address mode, the BKDBE becomes an enable for the second address
breakpoint. The BKMBH and BKMBL bits have no effect when in a dual address mode. BDM may be
entered by a breakpoint only if an internal signal from the BDM indicates background debug mode is
enabled. If BKPM = 1, then BKxRW, BKxRWE, BKMBH, and BKMBL have no meaning.
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1. Dual address-only breakpoints, each of which causes a software interrupt (SWI)
2. Single full-feature breakpoint which causes the part to enter background debug mode (BDM)
3. Dual address-only breakpoints, each of which causes the part to enter BDM
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Breakpoints are not allowed if the BDM mode is already active. Active mode means the CPU is
executing out of the BDM ROM.
BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. This is
important because even if the ENABLE bit in the BDM is negated, the CPU actually does execute
the BDM ROM code. It checks the ENABLE and returns if not set. If the BDM is not serviced by the
monitor, then the breakpoint would be re-asserted when the BDM returns to normal CPU flow.
There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled.
Breakpoints are not allowed if the BDM is already active. Active mode means the CPU is executing
out of the BDM ROM.
BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. This is
important because even if the ENABLE bit in the BDM is negated, the CPU actually does execute
the BDM ROM code. It checks the ENABLE and returns if not set. If the BDM is not serviced by the
monitor, then the breakpoint would be re-asserted when the BDM returns to normal CPU flow.
There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled.
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor