MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 64

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Central Processor Unit (CPU)
3.6 Indexed Addressing Modes
The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index
register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the
instruction opcode. The postbyte and extensions do these tasks:
64
Addressing Mode
•
•
•
•
Indexed-Indirect
Indexed-Indirect
D accumulator
16-bit offset
Specify which index register is used
Determine whether a value in an accumulator is used as an offset
Enable automatic pre- or post-increment or decrement
Specify use of 5-bit, 9-bit, or 16-bit signed offsets
offset
rr0nnnnn
111rr0zs
111rr011
rr1pnnnn
111rr1aa
111rr111
rr: 00 = X, 01 = Y, 10 = SP, 11 = PC
Code (xb)
Postbyte
INST [oprx16,xysp]
Table 3-1. Addressing Mode Summary (Continued)
,r
n,r
–n,r
n,r
–n,r
[n,r]
n,–r
n,r–
A,r
B,r
D,r
[D,r]
Source Format
Source Code
INST [D,xysp]
Syntax
Table 3-2. Summary of Indexed Operations
n,+r
n,r+
M68HC12B Family Data Sheet, Rev. 9.1
5-bit constant offset n = –16 to +15
r can specify X, Y, SP, or PC
Constant offset (9- or 16-bit signed)
z:0 = 9-bit with sign in LSB of postbyte(s)
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify X, Y, SP, or PC
16-bit offset indexed-indirect
rr can specify X, Y, SP, or PC
Auto pre-decrement/increment
or Auto post-decrement/increment;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
rr can specify X, Y, or SP (PC not a valid choice)
Accumulator offset (unsigned 8-bit or 16-bit)
aa:00 = A
rr can specify X, Y, SP, or PC
Accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
1 = 16-bit
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
Abbreviation
[D,IDX]
[IDX2]
Pointer to operand is found at
16-bit constant offset from x, y, sp, or pc
(16-bit offset in two extension bytes)
Pointer to operand is found at
x, y, sp, or pc plus the value in D
Comments
Description
Freescale Semiconductor