MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 298

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Development Support
18.3.6 BDM Status Register
This register can be read or written by BDM commands or firmware.
ENBDM — Enable BDM Bit (permit active background debug mode)
BDMACT — Background Mode Active Status Bit
ENTAG — Instruction Tagging Enable Bit
SDV — Shifter Data Valid Bit
TRACE
18.3.7 BDM Shifter Register
The 16-bit SHIFTER register contains data being received or transmitted via the serial interface. It is also
used by the BDM firmware for temporary storage. The register can be read or written in all modes but is
not normally accessed by users.
298
Set by the TAGGO instruction and cleared when BDM is entered.
Shows that valid data is in the serial interface shift register. Used by firmware-based instructions.
Asserted by the TRACE1 instruction
0 = BDM cannot be made active (hardware commands still allowed).
1 = BDM can be made active to allow firmware commands.
0 = BDM not active
1 = BDM active and waiting for serial commands
0 = Tagging not enabled, or BDM active
1 = Tagging active (BDM cannot process serial commands while tagging is active.)
0 = No valid data
1 = Valid data
Single-Chip Peripheral:
Reset:
Address: $FF02
Address: $FF03
Read:
Write:
Reset:
Read:
Write:
Address: $FF01
Reset:
Read:
Write:
Bit 7
Bit 7
S15
S7
0
0
ENBDM
Bit 7
Figure 18-7. BDM Shifter Register (SHIFTER)
Figure 18-6. BDM Status Register (STATUS)
0
1
S14
S6
6
0
6
0
EDMACT
M68HC12B Family Data Sheet, Rev. 9.1
6
0
0
S13
S5
5
0
5
0
ENTAG
5
0
0
S12
S4
4
0
4
0
SDV
4
0
0
S11
S3
3
0
3
0
TRACE
3
0
0
S10
S2
2
0
2
0
2
0
0
0
S9
S1
1
0
1
0
1
0
0
0
Freescale Semiconductor
Bit 0
Bit 0
S8
S0
0
0
Bit 0
0
0
0