MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 134

IC MCU 64K FLASH 4K RAM 80-QFP

MC9S12C64CFUE

Manufacturer Part Number
MC9S12C64CFUE
Description
IC MCU 64K FLASH 4K RAM 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12C64CFUE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
60
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
80PQFP
Family Name
HCS12
Maximum Speed
25 MHz
Operating Supply Voltage
2.5|5 V
Height
2.4 mm
Length
14 mm
Supply Voltage (max)
2.75 V, 5.5 V
Supply Voltage (min)
2.35 V, 2.97 V
Width
14 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Chapter 4 Multiplexed External Bus Interface (MEBIV3)
4.3.1
4.3.2
4.3.2.1
134
Module Base + 0x0000
Starting address location affected by INITRG register setting.
Emulation Narrow with
IVIS, and Peripheral
Expanded Narrow AB15 and
Expanded Wide,
Address
0x00032
0x00033
0x000A
0x000B
0x000C
0x000D
0x000E
0x001E
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000F
Offset
Single Chip
Module Memory Map
Register Descriptions
Port A Data Register (PORTA)
Reset
W
R
Port A Data Register (PORTA)
Port B Data Register (PORTB)
Data Direction Register A (DDRA)
Data Direction Register B (DDRB)
Reserved
Reserved
Reserved
Reserved
Port E Data Register (PORTE)
Data Direction Register E (DDRE)
Port E Assignment Register (PEAR)
Mode Register (MODE)
Pull Control Register (PUCR)
Reduced Drive Register (RDRIV)
External Bus Interface Control Register (EBICTL)
Reserved
IRQ Control Register (IRQCR)
Port K Data Register (PORTK)
Data Direction Register K (DDRK)
DB15/DB7
AB/DB15
Bit 7
PA7
0
7
Figure 4-2. Port A Data Register (PORTA)
DB14/DB6
AB14 and
AB/DB14
PA6
MC9S12C-Family / MC9S12GC-Family
6
0
6
Table 4-2. MEBI Memory Map
DB13/DB5
AB13 and
AB/DB13
PA5
5
0
5
Rev 01.24
Use
DB12/DB4
AB12 and
AB/DB12
PA4
4
4
0
DB11/DB3
AB11 and
AB/DB11
PA3
3
0
3
DB10/DB2
AB10 and
AB/DB10
PA2
2
0
2
Freescale Semiconductor
DB9/DB1
AB9 and
AB/DB9
PA1
Access
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
DB8/DB0
AB8 and
AB/DB8
Bit 0
PA0
0
0

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