MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 449

IC MCU 64K FLASH 4K RAM 80-QFP

MC9S12C64CFUE

Manufacturer Part Number
MC9S12C64CFUE
Description
IC MCU 64K FLASH 4K RAM 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12C64CFUE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
60
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
80PQFP
Family Name
HCS12
Maximum Speed
25 MHz
Operating Supply Voltage
2.5|5 V
Height
2.4 mm
Length
14 mm
Supply Voltage (max)
2.75 V, 5.5 V
Supply Voltage (min)
2.35 V, 2.97 V
Width
14 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number:
MC9S12C64CFUE
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Quantity:
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Part Number:
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15.3.2.9
Read: Anytime
Write: Anytime.
Freescale Semiconductor
Module Base + 0x000A
Module Base + 0x000B
EDGnB
EDGnA
Reset
Reset
Field
7:0
W
W
R
R
EDG7B
EDG3B
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
0
0
7
7
EDG7A
EDG3A
0
0
6
6
EDGnB
Table 15-13. Edge Detector Circuit Configuration
Figure 15-16. Timer Control Register 3 (TCTL3)
Figure 15-17. Timer Control Register 4 (TCTL4)
0
0
1
1
Table 15-12. TCTL3/TCTL4 Field Descriptions
EDG6B
EDG2B
MC9S12C-Family / MC9S12GC-Family
EDGnA
0
0
5
5
0
1
0
1
EDG6A
EDG2A
Capture on any edge (rising or falling)
Rev 01.24
0
0
4
4
Capture on falling edges only
Capture on rising edges only
Description
Capture disabled
Configuration
Chapter 15 Timer Module (TIM16B8CV1) Block Description
EDG5B
EDG1B
0
0
3
3
EDG5A
EDG1A
0
0
2
2
EDG4B
EDG0B
0
0
1
1
EDG4A
EDG0A
0
0
0
0
449

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