MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 64

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.7.4
The VREGEN input mentioned in the VREG section is device internal, connected internally to V
1.7.5
In the 80-pin QFP package versions, both internal V
sides of the device as two pin pairs (V
internally. V
80-pin package to employ better supply routing and further decoupling.
1.7.6
The low voltage reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset.
1.7.7
In the 48- and 52-pin package versions, the V
1.7.8
The MODRR register within the PIM allows for mapping of PWM channels to port T in the absence of
port P pins for the low pin count packages. For the 80QFP package option it is recommended not to use
MODRR since this is intended to support PWM channel availability in low pin count packages. Note that
when mapping PWM channels to port T in an 80QFP option, the associated PWM channels are then
mapped to both port P and port T. .
1.7.9
The port AD pins interface to the PIM module. However, the port pin digital state can be read from either
the PORTAD register in the ATD register map or from the PTAD register in the PIM register map.
In order to read a digital pin value from PORTAD the corresponding ATDDIEN bit must be set and the
corresponding DDRDA bit cleared. If the corresponding ATDDIEN bit is cleared then the pin is configured
as an analog input and the PORTAD bit reads back as "1".
In order to read a digital pin value from PTAD, the corresponding DDRAD bit must be cleared, to
configure the pin as an input.
Furthermore in order to use a port AD pin as an analog input, the corresponding DDRAD bit must be
cleared to configure the pin as an input
64
VREGEN
V
Clock Reset Generator And VREG Interface
Analog-to-Digital Converter
MODRR Register Port T And Port P Mapping
Port AD Dependency On PIM And ATD Registers
SS1
DD1
If the voltage regulator is shut down by connecting V
LVRF flag in the CRG flags register (CRGFLG) is undefined.
and V
, V
DD2
SS2
are connected together internally. The extra pin pair enables systems using the
, V
SS1
, V
MC9S12C-Family / MC9S12GC-Family
DD1
SS2
, V
SS1
RL
Rev 01.24
& V
pad is bonded internally to the V
NOTE
DD
DD2
and V
, V
SS2
SS
). V
of the 2.5V domain are bonded out on 2
DD1
DDR
and V
to ground then the
DD2
SSA
are connected together
Freescale Semiconductor
pin.
DDR
.