MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 478

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 17 16 Kbyte Flash Module (S12FTS16KV1)
17.3.2.4
The FCNFG register enables the Flash interrupts and gates the security backdoor key writes.
CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable.
KEYACC is only writable if the KEYEN bit in the FSEC register is set to the enabled state (see
17.3.2.2).
17.3.2.5
The FPROT register defines which Flash sectors are protected against program or erase.
The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0.
FPHS[1:0] can be written anytime until FPHDIS is cleared. The FPROT register is loaded from Flash
address 0xFF0D during the reset sequence, indicated by F in
478
Module Base + 0x0003
Module Base + 0x0004
KEYACC
Reset
CBEIE
Reset
Field
CCIE
7
6
5
W
W
R
R
FPOPEN
CBEIE
Command Buffer Empty Interrupt Enable — The CBEIE bit enables the interrupts in case of an empty
command buffer in the Flash module.
0 Command Buffer Empty interrupts disabled
1 An interrupt will be requested whenever the CBEIF flag is set (see
Command Complete Interrupt Enable — The CCIE bit enables the interrupts in case of all commands being
completed in the Flash module.
0 Command Complete interrupts disabled
1 An interrupt will be requested whenever the CCIF flag is set (see
Enable Security Key Writing.
0 Flash writes are interpreted as the start of a command write sequence
1 Writes to the Flash array are interpreted as a backdoor key while reads of the Flash array return invalid data
Flash Configuration Register (FCNFG)
Flash Protection Register (FPROT)
F
0
7
7
= Unimplemented or Reserved
CCIE
NV6
0
F
6
6
Figure 17-7. Flash Configuration Register (FCNFG)
Figure 17-8. Flash Protection Register (FPROT)
Table 17-7. FCNFG Field Descriptions
KEYACC
FPHDIS
MC9S12C-Family / MC9S12GC-Family
0
F
5
5
FPHS1
Rev 01.24
0
0
F
4
4
Description
FPHS0
Figure
F
0
0
3
3
17-8.
Section
Section
NV2
0
0
F
2
2
17.3.2.6)
17.3.2.6)
Freescale Semiconductor
NV1
0
0
F
1
1
Section
NV0
F
0
0
0
0