MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 271

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The sequence for clock quality check is shown in
1. A Clock Monitor Reset will always set the SCME bit to logical’1’
Freescale Semiconductor
POR
check window
Clock OK
or clock monitor reset
check the OSCCLK signal.
The clock quality checker enables the PLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running PLL (f
during pseudo-stop mode or wait mode
LVR
Remember that in parallel to additional actions caused by self-clock mode
osc ok
num=0
active?
SCM
?
yes
no
exit full stop
no
yes
Figure 9-20. Sequence for Clock Quality Check
CM fail
Switch to OSCCLK
MC9S12C-Family / MC9S12GC-Family
1
handling the clock quality checker continues to
num=num+1
Exit SCM
num<50
?
yes
Rev 01.24
NOTE
NOTE
Clock Monitor Reset
Enter SCM
Figure
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
no
9-20.
yes
SCM
) and an active VREG
SCME=1
active?
SCM
?
no
yes
no
num=50
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