MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 313

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Module Base + 0x001C (CANIDMR4)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
AM[7:0]
Field
7:0
Reset
Reset
Reset
Reset
Figure 10-22. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
W
W
W
W
R
R
R
R
0x001D (CANIDMR5)
0x001E (CANIDMR6)
0x001F (CANIDMR7)
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
AM7
AM7
AM7
AM7
0
0
0
0
7
7
7
7
Table 10-22. CANIDMR4–CANIDMR7 Register Field Descriptions
AM6
AM6
AM6
AM6
6
0
6
0
6
0
6
0
MC9S12C-Family / MC9S12GC-Family
AM5
AM5
AM5
AM5
0
0
0
0
5
5
5
5
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
Rev 01.24
AM4
AM4
AM4
AM4
4
0
4
0
4
0
4
0
Description
AM3
AM3
AM3
AM3
0
0
0
0
3
3
3
3
AM2
AM2
AM2
AM2
2
0
2
0
2
0
2
0
AM1
AM1
AM1
AM1
0
0
0
0
1
1
1
1
AM0
AM0
AM0
AM0
0
0
0
0
0
0
0
0
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