MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 253

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2
This section lists and describes the signals that connect off chip.
9.2.1
These pins provides operating voltage (V
the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required V
and V
9.2.2
A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter
to eliminate the VCO input ripple. The value of the external filter network and the reference frequency
determines the speed of the corrections and the stability of the PLL. Refer to the device overview chapter
for calculation of PLL loop filter (XFC) components. If PLL usage is not required the XFC pin must be
tied to V
Freescale Semiconductor
1
Refer to the device overview section for availability of the low-voltage reset feature.
SSPLL
XCLKS
EXTAL
XTAL
DDPLL
External Signal Description
RESET
V
V
V
XFC — PLL Loop Filter Pin
must be connected properly.
XFC
DDPLL
SSPLL
DDPLL
Regulator
Monitor
Oscil-
.
Voltage
Clock
lator
, V
SSPLL
OSCCLK
PLL
CRG
Power-on Reset
Low Voltage Reset
— PLL Operating Voltage, PLL Ground
MC9S12C-Family / MC9S12GC-Family
PLLCLK
Figure 9-1. CRG Block Diagram
CM fail
DDPLL
) and ground (V
Rev 01.24
Clock and Reset
1
Clock Quality
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
COP
Registers
Control
Checker
Generator
Reset
SSPLL
RTI
) for the PLL circuitry. This allows
Real-Time Interrupt
PLL Lock Interrupt
Self-Clock Mode
Oscillator Clock
System Reset
Core Clock
Bus Clock
Interrupt
DDPLL
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