DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 100

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.13
The BERT (Bit Error Rate Tester) block can generate and detect both pseudorandom and repeating bit patterns. It
is used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers.
The registers related to the configure, control, and status of the BERT are shown in
Table 9-45. Registers Related to Configure, Control, and Status of BERT
Global BERT Interrupt Status Register 1
(GBISR1)
Global BERT Interrupt Mask Register 1
(GBIMR1)
Receive Expansion Port Control Register
(RXPC)
Receive BERT Port Bit Suppress Register
(RBPBS)
Receive BERT Port Channel Select
Registers 1 to 4 (RBPCS1–RBPCS4)
Transmit Expansion Port Control Register
(TXPC)
Transmit BERT Port Bit Suppress Register
(TBPBS)
Transmit BERT Port Channel Select
Registers 1 to 4 (TBPCS1–TBPCS4)
BERT Alternating Word Count Rate Register
(BAWC)
BERT Repetitive Pattern Set Register 1
(BRP1)
BERT Repetitive Pattern Set Register 2
(BRP2)
BERT Repetitive Pattern Set Register 3
(BRP3)
BERT Repetitive Pattern Set Register 4
(BRP4)
BERT Control Register 1 (BC1)
BERT Control Register 2 (BC2)
BERT Bit Count Register 1 (BBC1)
BERT Bit Count Register 2 (BBC2)
BERT Bit Count Register 3 (BBC3)
BERT Bit Count Register 4 (BBC4)
BERT Error Count Register 1 (BEC1)
BERT Error Count Register 2 (BEC2)
BERT Error Count Register 3 (BEC3)
BERT Status Register (BSR)
BERT Status Interrupt Mask Register (BSIM)
BERT Control Register 3 (BC3)
BERT Real-Time Status Register (BRSR)
BERT Latched Status Register 1 (BLSR1)
BERT Status Interrupt Mask Register 1
(BSIM1)
BERT Latched Status Register 2 (BLSR2)
BERT Status Interrupt Mask Register 2
(BSIM2)
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer N = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
Bit Error-Rate Test Function (BERT)
REGISTER
ADDRESSES
0D4h, 0D5h,
1D4h, 1D5h,
0D6h, 0D7h
1D6h, 1D7h
FRAMER 1
100 of 312
00FDh
00FAh
110Ah
110Bh
110Ch
110Dh
110Eh
1100h
1101h
1102h
1103h
1104h
1105h
1106h
1107h
1108h
1109h
110Fh
1400h
1401h
1402h
1403h
1404h
1405h
08Ah
08Bh
18Ah
18Bh
When any of the 8 BERTs issue an interrupt, a
bit is set.
When any of the 8 BERTs issue an interrupt, a
bit is set.
Enable for the receiver BERT.
Bit suppression for the receive BERT.
Channels to be enabled for the framer to accept
data from the BERT pattern generator.
Enable for the transmitter BERT.
Bit suppression for the transmit BERT.
Channels to be enabled for the framer to accept
data from the transmit BERT pattern generator.
BERT alternating pattern count register.
BERT repetitive pattern set register 1.
BERT repetitive pattern set register 2.
BERT repetitive pattern set register 3.
BERT repetitive pattern set register 4.
Pattern selection and misc control.
BERT bit pattern length control.
Increments for BERT bit clocks.
BERT bit counter.
BERT bit counter.
BERT bit counter.
BERT error counter.
BERT error counter.
BERT error counter.
Denotes synchronization loss and other status.
BERT interrupt mask.
Pattern selection and misc control.
Denotes synchronization loss and other status.
Denotes synchronization loss and other status.
BERT interrupt mask.
BERT error status.
BERT interrupt mask.
Table
FUNCTION
9-45.