DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 305

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
See
14.1.1
Upon power-up, the TAP Controller will be in the Test-Logic-Reset state. The instruction register will contain the
IDCODE instruction. All system logic of the device will operate normally.
14.1.2
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction Register and test
registers will remain idle.
14.1.3
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the
Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the
controller to the Select-IR-Scan state.
14.1.4
Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does
not call for a parallel load or the selected register does not allow parallel loads, the Test Register remains at its
current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is LOW or it goes to
the Exit1-DR state if JTMS is HIGH.
14.1.5
The test data register selected by the current instruction is connected between JTDI and JTDO and will shift data
one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current
instruction is not placed in the serial path, it maintains its previous state.
14.1.6
While in this state, a rising edge on JTCLK puts the controller in the Update-DR state, which terminates the
scanning process if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW puts the controller in the Pause-DR
state.
14.1.7
Shifting of the test registers is halted while in this state. All test registers selected by the current instruction retain
their previous state. The controller remains in this state while JTMS is LOW. A rising edge on JTCLK with JTMS
HIGH puts the controller in the Exit2-DR state.
14.1.8
A rising edge on JTCLK with JTMS HIGH while in this state puts the controller in the Update-DR state and
terminates the scanning process. A rising edge on JTCLK with JTMS LOW enters the Shift-DR state.
14.1.9
A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the test
registers into the data output latches. This prevents changes at the parallel output due to changes in the shift
register.
14.1.10
All test registers retain their previous state. The instruction register remains unchanged during this state. With
JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence
Figure
TAP Controller State Machine
14-2.
Test-Logic-Reset
Run-Test-Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-Scan
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