DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 312

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0
REVISION
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
022007
060607
080607
103008
DATE
DOCUMENT REVISION HISTORY
New Product Release.
In the Absolute Maximum Ratings portion of Section 12, added Note 1 stating
that specifications to -40 ° C are guaranteed by design (GBD) and not production
tested.
Updated data sheet to reflect new features with B1 die revision:
HDLC-256 Controller—introduced in Section 9.10 and described in Section
9.10.3.
Extended BERT Registers—introduced in Section 9.13 and defined in Section
10.6.1.
Removed commercial temperature range product option from the Ordering
Information table and Operating Parameters (Section 12).
Added content to TCLKn pin description (Section 8.1).
Clarified how Read Bar/Data-Strobe Bar and Write Bar/ Read-Write Bar function
in Intel and Motorola bus modes (Section 8.1).
Added instruction in Step 5 of the Example Device Initialization and Sequence
(Section 9.4.1) to increase the frequency of the internally generated clock which
is supplied to the framers.
Added definition for Receive Master Mode Register bit 5 (RMMR.5) which, when
set, disables the receive-side synchronizer in the framer. This feature is new with
revision B1.
Replaced package drawing with table providing link to package drawing (Section
16).
© 2008 Maxim Integrated Products
DESCRIPTION
312 of 312
DS26518 8-Port T1/E1/J1 Transceiver
75, 77, 101, 259
CHANGED
PAGES
267
165
311
21
25
34
—
1