DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 53

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.9.3
The DS26518 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries
within the incoming NRZ data stream at TSERn. The TFM (TCR3.2) control bit determines whether the transmit
synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are
located in the
synchronization has occurred, and a real-time bit (LOF) which is set high when the synchronizer is searching for
frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INTB.
Note that when the transmit synchronizer is used, the TSYNCn signal should be set as an output (TSIO = 1) and
the recovered frame-sync pulse will be output on this signal. The recovered CRC-4 multi-frame sync pulse will be
output if enabled with TIOCR.0 (TSM = 1).
Other key points concerning the E1 transmit synchronizer:
The Tx synchronizer cannot search for the CAS multiframe.
synchronizer.
Table 9-16. Registers Related to the Transmit Synchronizer
Transmit Synchronizer Control Register
(TSYNCC)
Transmit Control Register 3 (TCR3)
Transmit Latched Status Register 3
(TLS3)
Transmit Interrupt Mask Register 3
(TIM3)
Transmit I/O Configuration Register
(TIOCR)
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
1) The Tx synchronizer is not operational when the transmit elastic store is enabled, including IBO modes.
2) The Tx synchronizer does not perform CRC-6 alignment verification (ESF mode) and does not verify
T1 Transmit Synchronizer
CRC-4 codewords.
TSYNCC
REGISTER
register. The latched status bit TLS3.0 (LOFD) is provided to indicate that a loss of frame
ADDRESSES
FRAMER 1
18Eh
1A2h
183h
192h
184h
53 of 312
Table 9-16
TSYNCn should be set as an output.
Resynchronization control for the transmit
synchronizer.
TFM bit selects between D4 and ESF for the
transmit synchronizer.
Provides latched status for the transmit
synchronizer.
Provides mask bits for the TLS3 status.
shows the registers related to the transmit
FUNCTION