DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 179

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in these register are latched. This register does not create interrupts. See
Bit 5: Change of Frame Alignment Event (COFA). Set when the last resync resulted in a change of frame or
multiframe alignment.
Bit 4: Eight Zero Detect Event (8ZD). Set when a string of at least eight consecutive zeros (regardless of the
length of the string) have been received at RRINGn and RTIPn.
Bit 3: Sixteen Zero Detect Event (16ZD). Set when a string of at least sixteen consecutive zeros (regardless of
the length of the string) have been received at RRINGn and RTIPn.
Bit 2: Severely Errored Framing Event (SEFE). Set when 2 out of 6 framing bits (Ft or FPS) are received in error.
Bit 1: B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RRINGn and RTIPn
independent of whether the B8ZS mode is selected or not. Useful for automatically setting the line coding.
Bit 0: Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched. Bits 0 to 3 can cause interrupts. There is no associated real-time register. See
for T1 Mode.
Bit 6: CRC Resync Criteria Met Event (CRCRC). Set when 915:1000 codewords are received in error.
Bit 5: CAS Resync Criteria Met Event (CASRC). Set when 2 consecutive CAS MF alignment words are received
in error.
Bit 4: FAS Resync Criteria Met Event (FASRC). Set when 3 consecutive FAS words are received in error.
Bit 3: Receive Signaling All Ones Event (RSA1). Set when the contents of time slot 16 contains fewer than three
zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.
Bit 2: Receive Signaling All Zeros Event (RSA0). Set when over a full MF, time slot 16 contains all zeros.
Bit 1: Receive CRC-4 Multiframe Event (RCMF). Set on CRC-4 multiframe boundaries; will continue to be set
every 2ms on an arbitrary boundary if CRC-4 is disabled.
Bit 0: Receive Align Frame Event (RAF). Set approximately every 250 μ s to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
—-
—
7
0
7
0
RLS2 (T1 Mode)
Receive Latched Status Register 2
091h + (200h x (n - 1)) : where n = 1 to 8
RLS2 (E1 Mode)
E1 Receive Latched Status Register 2
091h + (200h x (n - 1)) : where n = 1 to 8
CRCRC
—
6
0
6
0
CASRC
COFA
5
0
5
0
FASRC
179 of 312
8ZD
0
0
4
4
RSA1
16ZD
3
0
3
0
RLS2
SEFE
RSA0
2
0
2
0
for E1 Mode.
RCMF
B8ZS
1
0
1
0
FBE
RAF
RLS2
0
0
0
0