DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 75

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9-37. Registers Related to the HDLC-64
Receive HDLC-64 Control Register (RHC)
Receive HDLC-64 Bit Suppress Register
(RHBSE)
Receive HDLC-64 FIFO Control Register
(RHFC)
Receive HDLC-64 Packet Bytes Available
Register (RHPBA)
Receive HDLC-64 FIFO Register (RHF)
Receive Real-Time Status Register 5
(HDLC-64) (RRTS5)
Receive Latched Status Register 5
(HDLC-64) (RLS5)
Receive Interrupt Mask Register 5
(HDLC-64) (RIM5)
Transmit HDLC-64 Control Register 1 (THC1)
Transmit HDLC-64 Bit Suppress Register
(THBSE)
Transmit HDLC-64 Control Register 2 (THC2)
Transmit HDLC-64 FIFO Control Register
(THFC)
Transmit Real-Time Status Register 2
(HDLC-64) (TRTS2)
Transmit Latched Status Register 2
(HDLC-64) (TLS2)
Transmit Interrupt Mask Register 2
(HDLC-64) (TIM2)
Transmit HDLC-64 FIFO Buffer Available
Register (TFBA)
Transmit HDLC-64 FIFO Register (THF)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
9.10.1.1
Control of the transmit and receive FIFOs is accomplished via the Receive HDLC-64 FIFO Control (RHFC) and
Transmit HDLC-64 FIFO Control (THFC) registers. The FIFO control registers set the watermarks for the FIFO.
When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) will be set. RHWM and TLWM
are real-time bits and will remain set as long as the FIFO’s write pointer is above the watermark. When the transmit
FIFO empties below the low watermark, the TLWM bit in the
and will remain set as long as the transmit FIFO’s write pointer is below the watermark. If enabled, this condition
can also cause an interrupt via the INTB pin.
If the receive HDLC-64 FIFO does overrun the current packet being processed is dropped and the receive FIFO is
emptied. The packet status bits in
HDLC-64 FIFO Control
REGISTER
RRTS5
and RLS5.5 (ROVR) indicate an overrun.
ADDRESSES
FRAMER 1
75 of 312
0B5h
0B6h
0B4h
0A4h
1B1h
1A1h
1B3h
1B4h
010h
011h
087h
094h
110h
111h
113h
187h
191h
TRTS2
Mapping of the HDLC-64 to DS0 or FDL, Sa
bits.
Receive HDLC-64 bit suppression register.
Determines the watermark of the receive
HDLC-64 FIFO.
Tells the user how many bytes are available in
the receive HDLC-64 FIFO.
The actual FIFO data.
Indicates the FIFO status.
Latched status.
Interrupt mask for interrupt generation for the
latched status.
Miscellaneous transmit HDLC-64 control.
Transmit HDLC-64 bit suppress for bits not to
be used.
HDLC-64 to DS0 channel selection and other
control.
Used to control the transmit HDLC-64 FIFO.
Indicates the real-time status of the transmit
HDLC-64 FIFO.
Indicates the FIFO status.
Interrupt mask for the latched status.
Indicates the number of bytes that can be
written into the transmit FIFO.
Transmit HDLC-64 FIFO.
register will be set. TLWM is a real-time bit
FUNCTION