DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 8

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS26518 8-Port T1/E1/J1 Transceiver
Table 10-1. Register Address Ranges (in Hex)....................................................................................................... 102
Table 10-2. Global Register List .............................................................................................................................. 103
Table 10-3. Framer Register List ............................................................................................................................. 104
Table 10-4. LIU Register List ................................................................................................................................... 111
Table 10-5. BERT Register List ............................................................................................................................... 112
Table 10-6. HDLC-256 Register List........................................................................................................................ 113
Table 10-7. Global Register Bit Map........................................................................................................................ 114
Table 10-8. Framer Register Bit Map ...................................................................................................................... 115
Table 10-9. LIU Register Bit Map ............................................................................................................................ 125
Table 10-10. BERT Register Bit Map ...................................................................................................................... 126
Table 10-11. HDLC-256 Register Bit Map............................................................................................................... 127
Table 10-12. Global Register Set ............................................................................................................................ 128
Table 10-13. Output Status Control ......................................................................................................................... 129
Table 10-14. Master Clock Input Selection.............................................................................................................. 132
Table 10-15. Backplane Reference Clock Select .................................................................................................... 133
Table 10-16. Device ID Codes in this Product Family ............................................................................................. 138
Table 10-17. LIU Register Set ................................................................................................................................. 240
Table 10-18. Transmit Load Impedance Selection.................................................................................................. 242
Table 10-19. Transmit Pulse Shape Selection ........................................................................................................ 242
Table 10-20. Receive Level Indication .................................................................................................................... 247
Table 10-21. Receive Impedance Selection............................................................................................................ 248
Table 10-22. Receiver Sensitivity Selection with Monitor Mode Disabled............................................................... 249
Table 10-23. Receiver Sensitivity Selection with Monitor Mode Enabled ............................................................... 249
Table 10-24. BERT Register Set ............................................................................................................................. 250
Table 10-25. BERT Pattern Select .......................................................................................................................... 252
Table 10-26. BERT Error Insertion Rate ................................................................................................................. 253
Table 10-27. BERT Repetitive Pattern Length Select ............................................................................................. 253
Table 10-28. Extended BERT Register Set............................................................................................................. 258
Table 10-29. Transmit-Side HDLC-256 Register Set .............................................................................................. 262
Table 10-30. Receive-Side HDLC-256 Register Set ............................................................................................... 267
Table 12-1. Recommended DC Operating Conditions ............................................................................................ 291
Table 12-2. Capacitance.......................................................................................................................................... 291
Table 12-3. Recommended DC Operating Conditions ............................................................................................ 291
Table 12-4. Thermal Characteristics........................................................................................................................ 292
Table 12-5. Transmitter Characteristics................................................................................................................... 292
Table 12-6. Receiver Characteristics....................................................................................................................... 292
Table 13-1. SPI Bus Mode Timing........................................................................................................................... 293
Table 13-2. AC Characteristics—Microprocessor Bus Timing ................................................................................ 295
Table 13-3. Receiver AC Characteristics ................................................................................................................ 298
Table 13-4. Transmit AC Characteristics................................................................................................................. 300
Table 13-5. JTAG Interface Timing.......................................................................................................................... 303
Table 14-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 308
Table 14-2. ID Code Structure................................................................................................................................. 309
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