DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 107

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0D8h–0DBh
0B7h–0BFh
0E0h–0EFh
0F0h–0FFh
ADDRESS
0CAh
0CBh
0CCh
0CDh
0CEh
0DCh
0DDh
0DEh
0AFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h
0C9h
0CFh
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D6h
0D7h
0DFh
0B0h
0B1h
0B2h
0B3h
0B4h
0B5h
0B6h
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
(Section 10.3)
T1RDNCD2
TDMWE1
TDMWE2
TDMWE3
TDMWE4
RGCCS1
RGCCS2
RGCCS3
RGCCS4
Registers
RBPCS1
RBPCS2
RBPCS3
RBPCS4
RCICE1
RCICE2
RCICE3
RCICE4
RHPBA
RBCS1
RBCS2
RBCS3
RBCS4
RCBR1
RCBR2
RCBR3
RCBR4
RHCS1
RHCS2
RHCS3
RHCS4
RRTS1
RRTS3
RRTS3
RRTS5
TDDS1
TDDS2
TJBE1
TJBE2
TJBE3
TJBE4
NAME
Global
RSI1
RSI2
RSI3
RSI4
RHF
—
—
—
—
—
Receive Down Code Definition Register 2 (T1 Mode Only)
Receive Real-Time Status Register 1
Reserved
Receive Real-Time Status Register 3 (T1 Mode)
Receive Real-Time Status Register 3 (E1 Mode)
Reserved
Receive Real-Time Status Register 5 (HDLC-64)
Receive HDLC-64 Packet Bytes Available Register
Receive HDLC-64 FIFO Register
Reserved
Receive Blank Channel Select Register 1
Receive Blank Channel Select Register 2
Receive Blank Channel Select Register 3
Receive Blank Channel Select Register 4 (E1 Mode Only)
Receive Channel Blocking Register 1
Receive Channel Blocking Register 2
Receive Channel Blocking Register 3
Receive Channel Blocking Register 4 (E1 Mode Only)
Receive-Signaling Reinsertion Enable Register 1
Receive-Signaling Reinsertion Enable Register 2
Receive-Signaling Reinsertion Enable Register 3
Receive-Signaling Reinsertion Enable Register 4 (E1 Mode Only)
Receive Gapped Clock Channel Select Register 1
Receive Gapped Clock Channel Select Register 2
Receive Gapped Clock Channel Select Register 3
Receive Gapped Clock Channel Select Register (E1 Mode Only)
Receive Channel Idle Code Enable Register 1
Receive Channel Idle Code Enable Register 2
Receive Channel Idle Code Enable Register 3
Receive Channel Idle Code Enable Register 4 (E1 Mode Only)
Receive BERT Port Channel Select Register 1
Receive BERT Port Channel Select Register 2
Receive BERT Port Channel Select Register 3
Receive BERT Port Channel Select Register 4 (E1 Mode Only)
Reserved
Receive HDLC-256 Channel Select Register 1
Receive HDLC-256 Channel Select Register 2
Receive HDLC-256 Channel Select Register 3
Receive HDLC-256 Channel Select Register 4 (E1 Mode Only)
Reserved
See the Global Register list in
“Reserved” in Framers 2 to 8.
Transmit Digital Milliwatt Enable Register 1 (T1 and E1 Modes)
Transmit Digital Milliwatt Enable Register 2 (T1 and E1 Modes)
Transmit Digital Milliwatt Enable Register 3 (T1 and E1 Modes)
Transmit Digital Milliwatt Enable Register 4 (T1 and E1 Modes)
Transmit Jammed Bit Eight Stuffing Register 1
Transmit Jammed Bit Eight Stuffing Register 2
Transmit Jammed Bit Eight Stuffing Register 3
Transmit Jammed Bit Eight Stuffing Register 4
Transmit DDS Zero Code Register 1
Transmit DDS Zero Code Register 2
FRAMER REGISTER LIST
107 of 312
DESCRIPTION
Table
10-2. Note that this space is
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
R
R
R
R
R