DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 266

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Transmit FIFO Overflow Latched (TFOL). This bit is set when a transmit FIFO overflow condition occurs.
Bit 4: Transmit FIFO Underflow Latched (TFUL). This bit is set when a transmit FIFO underflow condition
occurs. An underflow condition results in a loss of data.
Bit 3: Transmit Packet End Latched (TPEL). This bit is set when an end of packet is read from the transmit FIFO.
Bit 1: Transmit FIFO Empty Latched (TFEL). This bit is set when the TFE bit transitions from 0 to 1. Note: This
bit is also set when TH256CR1.TFRST is deasserted.
Bit 0: Transmit HDLC-256 Data Available Latched (THDAL). This bit is set when the THDA bit transitions from 0
to 1. Note: This bit is also set when TH256CR1.TFRST is deasserted.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Transmit FIFO Overflow Interrupt Enable (TFOIE). This bit enables an interrupt if the TFOL bit is set.
Bit 4: Transmit FIFO Underflow Interrupt Enable (TFUIE). This bit enables an interrupt if the TFUL bit is set.
Bit 3: Transmit Packet End Interrupt Enable (TPEIE). This bit enables an interrupt if the TPEL bit is set.
Bit 1: Transmit FIFO Empty Interrupt Enable (TFEIE). This bit enables an interrupt if the TFEL bit is set.
Bit 0: Transmit HDLC-256 Data Available Interrupt Enable (THDAIE). This bit enables an interrupt if the THDAL
bit is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
—
—
7
0
7
0
—
—
6
0
6
0
TH256SRL
Transmit HDLC-256 Status Register Latched
1506h + (20h x (n - 1)) : where n = 1 to 8
TH256SRIE
Transmit HDLC-256 Status Register Interrupt Enable
1508h + (20h x (n-1)) : where n = 1 to 8
TFOIE
TFOL
5
0
5
0
266 of 312
TFUIE
TFUL
0
0
4
4
TPEIE
TPEL
3
0
3
0
—
—
2
0
2
0
TFEIE
TFEL
1
0
1
0
THDAIE
THDAL
0
0
0
0