DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 261

IC TXRX T1/E1/J1 8PORT 256-CSBGA

DS26518GN+

Manufacturer Part Number
DS26518GN+
Description
IC TXRX T1/E1/J1 8PORT 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheets

Specifications of DS26518GN+

Number Of Drivers/receivers
8/8
Protocol
T1/E1/J1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All latched bits in this register can create interrupts.
Bit 2: BERT Bit Error Detected Event (BED). A latched bit that is set when a bit error is detected. The receive
BERT must be in synchronization for it to detect bit errors.
Bit 1: BERT Bit Counter Overflow Event (BBCO). A latched bit that is set when the 32-bit BERT bit counter
(BBC) overflows.
Bit 0: BERT Error Counter Overflow Event (BECO). A latched bit that is set when the 24-bit BERT error counter
(BEC) overflows.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 2: Bit Error Detected Event (BED)
Bit 1: BERT Bit Counter Overflow Event (BBCO)
Bit 0: BERT Error Counter Overflow Event (BECO)
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
7
0
7
0
BLSR2
BERT Latched Status Register 2
1404h + (10h x (n - 1)) : where n = 1 to 8
BSIM2
BERT Status Interrupt Mask Register 2
1405h + (10h x (n - 1)) : where n = 1 to 8
6
0
6
0
5
0
5
0
261 of 312
0
0
4
4
3
0
3
0
BED
BED
2
0
2
0
BBCO
BBCO
1
0
1
0
BECO
BECO
0
0
0
0

Related parts for DS26518GN+