DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 203
DS26518GN+
Manufacturer Part Number
DS26518GN+
Description
IC TXRX T1/E1/J1 8PORT 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Specifications of DS26518GN+
Number Of Drivers/receivers
8/8
Protocol
T1/E1/J1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Bits 7 to 0: BERT Port Channel Select Receive Channels 1 to 32 (CH[1:32])
Register Name:
Register Description:
Register Address:
Bit #
Name
Setting any of the CH[1:32] bits in the RHCS1 to RHCS4 registers enables the receive HDLC-256 clock for the
associated channel time, and allows mapping of the selected channel data into the HDLC-256 port. Multiple or all
channels may be selected simultaneously.
0 = Do not enable the receive BERT clock for the associated channel time, or map the selected channel
data out of the receive BERT port.
1 = Enable receive BERT clock for the associated channel time, and allow mapping of the selected
channel data out of the receive BERT port. Multiple or all channels may be selected simultaneously.
(MSB)
(MSB)
CH16
CH24
CH32
CH16
CH24
CH32
CH8
CH8
7
7
CH15
CH23
CH31
CH15
CH23
CH31
CH7
CH7
RBPCS1, RBPCS2, RBPCS3, RBPCS4
Receive BERT Port Channel Select Registers 1 to 4
0D4h, 0D5h, 0D6h, 0D7h + (200h x (n - 1)) : where n = 1 to 8
RHCS1, RHCS2, RHCS3, RHCS4
Receive HDLC-256 Channel Select Registers 1 to 4
0DCh, 0DDh, 0DEh, 0DFh + (200h x (n - 1)) : where n = 1 to 8
6
6
CH14
CH22
CH30
CH14
CH22
CH30
CH6
CH6
5
5
CH13
CH21
CH29
CH13
CH21
CH29
CH5
CH5
4
4
203 of 312
CH12
CH20
CH28
CH12
CH20
CH28
CH4
CH4
3
3
CH11
CH19
CH27
CH11
CH19
CH27
CH3
CH3
2
2
CH10
CH18
CH26
CH10
CH18
CH26
CH2
CH2
1
1
(LSB)
CH17
CH25
(LSB)
CH17
CH25
CH1
CH9
CH1
CH9
0
0
RHCS1
RBPCS1
RBPCS2
RBPCS3
RBPCS4 (E1
Mode Only)
RHCS2
RHCS3
RHCS4 (E1
Mode Only)
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