SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet
SAF1760BE/V1,557
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SAF1760BE/V1,557 Summary of contents
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SAF1760 Hi-Speed Universal Serial Bus host controller for embedded applications Rev. 01 — 9 November 2009 1. General description The SAF1760 is a Hi-Speed Universal Serial Bus (USB) host controller with a generic processor interface. It integrates one Enhanced Host ...
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... NXP Semiconductors I Generic processor interface, non-multiplexed and variable latency, with a configurable 32-bit or 16-bit external data bus; the processor interface can be defined as variable-latency or SRAM type (memory mapping) I Slave DMA support to reduce the load of the host system CPU during the data transfer ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name Description SAF1760BE LQFP128 plastic low profile quad flat package; 128 leads; body 14 SAF1760_1 Product data sheet Embedded Hi-Speed USB host controller Rev. 01 — 9 November 2009 SAF1760 Version 20 1.4 mm SOT425-1 © ...
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... NXP Semiconductors 5. Block diagram 47, 49, 51, 52 78, 80 DATA[15:0]/DATA[31:0] 82, 84, 86, 87 98, 100 to 103, 105 17 A[17:1] 106 CS_N 107 RD_N 108 WR_N 112 IRQ 114 DREQ DACK 116 USB FULL-SPEED AND LOW-SPEED DATA PATH PORT ROUTING OR CONTROL LOGIC + HOST AND HUB PORT STATUS ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. [1][2] Symbol OC3_N REF5V TEST1 GNDA REG1V8 V CC(5V0) V CC(5V0) GND(OSC) REG3V3 V CC(I/O) XTAL1 XTAL2 SAF1760_1 Product data sheet 1 SAF1760BE 38 Pin configuration (LQFP128); top view Pin description [3] Pin Type Description ...
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... NXP Semiconductors Table 2. Symbol CLKIN GNDD GND(RREF1) 15 RREF1 [4] GNDA DM1 GNDA DP1 PSW1_N GND(RREF2) 22 RREF2 [5] GNDA DM2 GNDA DP2 PSW2_N GND(RREF3) 29 RREF3 [6] GNDA DM3 GNDA DP3 PSW3_N GNDD DATA0 DATA1 DATA2 SAF1760_1 Product data sheet Pin description …continued [1][2] [3] Pin Type ...
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... NXP Semiconductors Table 2. Symbol V CC(I/O) DATA3 DATA4 DATA5 GNDD DATA6 DATA7 DATA8 V CC(I/O) DATA9 REG1V8 DATA10 DATA11 GNDC DATA12 GNDD DATA13 SAF1760_1 Product data sheet Pin description …continued [1][2] [3] Pin Type Description LQFP128 40 P digital supply voltage; 1. 3.6 V; connect a 100 nF decoupling capacitor; see ...
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... NXP Semiconductors Table 2. Symbol DATA14 DATA15 V CC(I/O) DATA16 DATA17 DATA18 GNDD DATA19 DATA20 DATA21 V CC(I/O) DATA22 DATA23 DATA24 GNDD DATA25 DATA26 SAF1760_1 Product data sheet Pin description …continued [1][2] [3] Pin Type Description LQFP128 57 I/O data bit 14 input and output bidirectional pad, push-pull input, 3-state output output drive, 3 ...
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... NXP Semiconductors Table 2. Symbol DATA27 V CC(I/O) DATA28 DATA29 DATA30 GNDD DATA31 TEST2 A1 V CC(I/O) A2 REG1V8 A3 A4 GNDC A5 GNDD SAF1760_1 Product data sheet Pin description …continued [1][2] [3] Pin Type Description LQFP128 74 I/O data bit 27 input and output bidirectional pad, push-pull input, 3-state output output drive, 3 ...
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... NXP Semiconductors Table 2. Symbol V CC(I/O) A9 A10 A11 A12 GNDD A13 A14 A15 A16 V CC(I/O) A17 CS_N RD_N WR_N GNDD BAT_ON_N n.c. IRQ n.c. DREQ SAF1760_1 Product data sheet Pin description …continued [1][2] [3] Pin Type Description LQFP128 94 P digital supply voltage; 1. 3.6 V; connect a 100 nF decoupling capacitor ...
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... NXP Semiconductors Table 2. Symbol V CC(I/O) DACK TEST3 REG1V8 SUSPEND/ WAKEUP_N TEST4 GNDC RESET_N GNDA TEST5 TEST6 TEST7 OC1_N OC2_N [1] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals. [2] All ground pins should normally be connected to a common ground plane. ...
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... NXP Semiconductors 7. Functional description 7.1 SAF1760 internal architecture: advanced NXP slave host controller and hub The EHCI block and the Hi-Speed USB hub block are the main components of the advanced NXP slave host controller. The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the SAF1760 is adapted from Universal Serial Bus Rev ...
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... NXP Semiconductors Fig 3. 7.1.1 Internal clock scheme and port selection The SAF1760 has three ports. Fig 4. Figure 4 enabled by software, if only port 1 or port 3 is used. No port needs to be disabled by external pull-up resistors, if not used. The DP and DM of the unused ports need not be externally pulled HIGH because there are internal pull-down resistors on each port that are enabled by default ...
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... NXP Semiconductors Table 3. Port connection scenarios Port configuration Port 1 One port (port 1) DP and DM are routed to USB connector One port (port 2) DP and DM are not connected (left open) One port (port 3) DP and DM are not connected (left open) Two ports (ports 1 ...
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... NXP Semiconductors A larger buffer also implies a larger amount of data can be transferred. The transfer, however, can be done over a longer period of time, to maintain the overall system performance. Each transfer of the USB data on the USB bus can span for few milliseconds before requiring further CPU intervention for data movement. ...
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... NXP Semiconductors Some of the design features are: • The address range of the internal RAM buffer is from 0400h to FFFFh. • The internal memory contains isochronous, interrupt and asynchronous PTDs, and respective defined payloads. • All accesses to the internal memory are double word aligned. ...
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... NXP Semiconductors Both the CPU interface logic and the USB host controller require access to the internal SAF1760 RAM at the same time. The internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing a maximum bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the CPU interface and the internal USB host controller ...
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... NXP Semiconductors Remark: Once 4000h is written to the Memory register for bank1, the bank select value determines the successive incremental addresses used to fetch data. That is, the fetching of data is independent of the address on A[15:0] lines. – Write the starting (read) address 4100h and bank2 = 10b to the Memory register. ...
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... NXP Semiconductors The DMA start address must be initialized in the respective register, and the subsequent transfers will automatically increment the internal SAF1760 memory address. A register or memory access or access to other system memory can occur in between DMA bursts, whenever the bus is released because DACK is de-asserted, without affecting the DMA transfer counter or the current address ...
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... NXP Semiconductors – Enable ENABLE_DMA (bit 1) of the DMA Configuration register to determine the assertion of DREQ immediately after setting the bit. After programming the preceding parameters, the systems DMA may be enabled, waiting for the DREQ to start the transfer or immediate transfer may be started. ...
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... NXP Semiconductors The IRQ generation rules that apply according to the preceding settings are: • event of interrupt occurs but the respective bit in the Interrupt Enable register is not set, then the respective Interrupt register bit is set but the interrupt signal is not asserted. An interrupt will be generated when interrupt is enabled and the respective bit in the Interrupt Enable register is set. • ...
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... NXP Semiconductors Table 5. PTD 7.5 Phase-Locked Loop (PLL) clock multiplier The internal PLL requires a 12 MHz input, which can MHz crystal MHz clock already existing in the system with a precision better than 50 use of a low-cost 12 MHz crystal that also minimizes ElectroMagnetic Interference (EMI). ...
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... NXP Semiconductors The SUSPEND/WAKEUP_N pin is a 3-state output also an input to the internal wake-up logic. When in suspend mode, the SAF1760 internal wake-up circuitry will sense the status of the SUSPEND/WAKEUP_N pin: • remains pulled-up, no wake-up is generated because a HIGH is sensed by the internal wake-up circuit. ...
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... NXP Semiconductors When using the integrated analog overcurrent detection, the range of the overcurrent detection voltage for the SAF1760 120 mV. Calculation of external components should be based on the 45 mV value, with the actual overcurrent detection threshold usually positioned in the middle of the interval. For an overcurrent limit of 500 mA per port, a PMOS transistor with R approximately 100 m is required PMOS transistor with a lower R analog overcurrent detection can be adjusted using a series resistor ...
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... NXP Semiconductors 7.8 Power supply Figure 7 (1) Each supply voltage pin must be connected to a 100 nF decoupling capacitor ( electrolytic or tantalum capacitor is required on any one of the pins 118. Fig 7. Figure 8 (1) Each supply voltage pin must be connected to a 100 nF decoupling capacitor ( electrolytic or tantalum capacitor is required on any one of the pins 118. ...
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... NXP Semiconductors 7.8.1 Hybrid mode Table 6 Table 6. Voltage V CC(5V0) V CC(I/O) In hybrid mode (see transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the suspend current CC(5V0) back on, before the resume programming sequence starts. (1) Each supply voltage pin must be connected to a 100 nF decoupling capacitor ( ...
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... NXP Semiconductors 7.9 Power-On Reset (POR) Figure 10 starts with a HIGH at t0. At t1, the detector will see the passing of the trip level V a delay element will add another t too short, less than 11 s, the PORP will not react and will remain LOW. A HIGH on PORP will be generated whenever REG1V8 drops below V (1) PORP = Power-On Reset Pulse ...
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... NXP Semiconductors 8. Registers Table 8 • All registers range from 0000h to 03FFh. These registers can be read or written as double word, which is 32-bit data. In case of a 16-bit data bus width, two subsequent accesses are necessary to complete the register read or write cycle. • Operational registers range from 0000h to 01FFh. Configuration registers range from 0300h to 03FFh ...
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... NXP Semiconductors Table 8. Address 0344h 0354h 0374h Interrupt registers 0310h 0314h 0318h 031Ch 0320h 0324h 0328h 032Ch 8.1 EHCI capability registers 8.1.1 CAPLENGTH register The bit description of the Capability Length (CAPLENGTH) register is given in Table 9. Bit 8.1.2 HCIVERSION register Table 10 (HCIVERSION) register. ...
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... NXP Semiconductors 8.1.3 HCSPARAMS register The Host Controller Structural Parameters (HCSPARAMS) register is a set of fields that are structural parameters. The bit allocation is given in Table 11. HCSPARAMS - Host Controller Structural Parameters register (address 0004h) bit allocation Bit 31 Symbol Reset 0 Access R Bit 23 Symbol Reset ...
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... NXP Semiconductors 8.1.4 HCCPARAMS register The Host Controller Capability Parameters (HCCPARAMS) register is a four byte register, and the bit allocation is given in Table 13. HCCPARAMS - Host Controller Capability Parameters register (address 0008h) bit allocation Bit 31 Symbol Reset 0 Access R Bit 23 Symbol Reset 0 Access R Bit ...
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... NXP Semiconductors 8.2 EHCI operational registers 8.2.1 USBCMD register The USB Command (USBCMD) register indicates the command to be executed by the serial host controller. Writing to this register causes a command to be executed. shows the USBCMD register bit allocation. Table 15. USBCMD - USB Command register (address 0020h) bit allocation ...
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... NXP Semiconductors 8.2.2 USBSTS register The USB Status (USBSTS) register indicates pending interrupts and various states of the host controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software clears register bits by writing ones to them. The bit allocation is given in Table 17 ...
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... NXP Semiconductors 8.2.3 USBINTR register The USB Interrupt (USBINTR) register is a read or write register located at 0028h. All the bits in this register are reserved. 8.2.4 FRINDEX register The Frame Index (FRINDEX) register is used by the host controller to index into the periodic frame list. The register updates every 125 s (once each microframe). Bits are used to select a particular entry in the periodic frame list during periodic schedule execution ...
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... NXP Semiconductors 8.2.5 CONFIGFLAG register The bit allocation of the Configure Flag (CONFIGFLAG) register is given in Table 21. CONFIGFLAG - Configure Flag register (address 0060h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access ...
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... NXP Semiconductors Table 23. PORTSC1 - Port Status and Control 1 register (address 0064h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol PIC[1:0] Reset 0 Access R Bit 7 Symbol SUSP FPR Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...
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... NXP Semiconductors Table 24. PORTSC1 - Port Status and Control 1 register (address 0064h) bit description Bit Symbol Description 2 PED Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable. 1 ECSC Connect Status Change: Logic 1 means change in ECCS. Logic 0 means no change. 0 ECCS Current Connect Status: Logic 1 indicates a device is present on the port. Logic 0 indicates no device is present ...
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... NXP Semiconductors respective memory space, would be checked, especially if only a few PTDs are defined. The LastPTD bit must be normally set to a higher position than any other position indicated by the NextPTDPointer from an active PTD. 8.2.10 INT PTD Done Map register The bit description of the register is given in Table 28 ...
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... NXP Semiconductors 8.2.13 ATL PTD Done Map register Table 31 Table 31. ATL PTD Done Map register (address 0150h) bit description Bit Symbol Access ATL_PTD_DONE_ R MAP[31:0] This register represents a direct map of the done status of the 32 PTDs. The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. Reading the Done Map register will clear all the bits that are set to logic 1, and the next reading will refl ...
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... NXP Semiconductors 8.3 Configuration registers 8.3.1 HW Mode Control register Table 34 Table 34. HW Mode Control - Hardware Mode Control register (address 0300h) bit allocation Bit 31 Symbol ALL_ATX_ RESET Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol ANA_DIGI_ OC Reset ...
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... NXP Semiconductors Table 35. HW Mode Control - Hardware Mode Control register (address 0300h) bit description Bit Symbol 5 DREQ_POL INTR_POL 1 INTR_LEVEL 0 GLOBAL_INTR_EN 8.3.2 Chip ID register Read this register to get the ID of the SAF1760. The upper word of the register contains the hardware version number and the lower word contains the chip ID. ...
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... NXP Semiconductors 8.3.4 SW Reset register Table 38 Table 38. SW Reset - Software Reset register (address 030Ch) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...
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... NXP Semiconductors 8.3.5 DMA Configuration register The bit allocation of the DMA Configuration register is given in Table 40. DMA Configuration register (address 0330h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access ...
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... NXP Semiconductors 8.3.6 Buffer Status register The Buffer Status register is used to indicate the HC that a particular PTD buffer (that is, ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets the Buffer Filled bit of a particular transfer in the Buffer Status register, the HC will start traversing through PTD headers that are not marked for skipping and are valid PTDs ...
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... NXP Semiconductors 8.3.7 ATL Done Timeout register The bit description of the ATL Done Timeout register is given in Table 44. ATL Done Timeout register (address 0338h) bit description Bit Symbol Access ATL_DONE_ R/W TIMEOUT[31:0] 8.3.8 Memory register The Memory register contains the base memory read address and the respective bank. ...
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... NXP Semiconductors 8.3.9 Edge Interrupt Count register Table 47 Table 47. Edge Interrupt Count register (address 0340h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value ...
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... NXP Semiconductors 8.3.10 DMA Start Address register This register defines the start address select for the DMA read and write operations. See Table 49 Table 49. DMA Start Address register (address 0344h) bit allocation Bit 31 Symbol Reset 0 Access W Bit 23 Symbol Reset 0 Access W Bit ...
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... NXP Semiconductors 8.3.11 Power-Down Control register This register is used to turn off power to the internal blocks of the SAF1760 to obtain maximum power savings. Table 51. Power-Down Control register (address 0354h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 1 Access R/W R/W ...
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... NXP Semiconductors Table 52. Power-Down Control register (address 0354h) bit description [1] Bit Symbol Description 10 VBATDET_PW V BAT R 0 — — reserved; write reset value 5 BIASEN Bias Circuits Powered: Controls the power to internal bias circuits. 0 — Internal bias circuits are not powered in suspend. 1 — Internal bias circuits are powered in suspend. ...
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... NXP Semiconductors 8.3.12 Port 1 Control register The values read from the lower 16 bits and the upper 16 bits of this register are always the same. Table 53 Table 53. Port 1 Control register (address 0374h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol PORT1_ ...
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... NXP Semiconductors 8.4 Interrupt registers 8.4.1 Interrupt register The bits of this register indicate the interrupt source, defining the events that determined the INT generation. Clearing the bits that were set because of the events listed is done by writing back logic 1 to the respective position. All bits must be reset before enabling new interrupt events ...
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... NXP Semiconductors Table 56. Interrupt register (address 0310h) bit description Bit Symbol Description reserved; write reset value 9 ISO_IRQ ISO IRQ: Indicates that an ISO PTD was completed, or the PTDs corresponding to the bits set in the ISO IRQ Mask AND or ISO IRQ Mask OR register bits combination were completed. The IRQ line will be asserted if the respective enable bit in the HCInterruptEnable register is set. 0 — ...
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... NXP Semiconductors 8.4.2 Interrupt Enable register This register allows enabling or disabling of the IRQ generation because of various events as described in Table 57. Interrupt Enable register (address 0314h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset ...
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... NXP Semiconductors Table 58. Interrupt Enable register (address 0314h) bit description Bit Symbol Description 6 CLKREADY_E Clock Ready Enable: Enables the IRQ assertion when internal clock signals are running stable. Useful after wake-up. 0 — No IRQ will be generated after a CLKREADY_E event. 1 — IRQ will be generated after a CLKREADY_E event. ...
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... NXP Semiconductors Table 61. ATL IRQ Mask OR register (address 0320h) bit description Bit Symbol Access Value ATL_IRQ_MASK R/W _OR[31:0] 8.4.6 ISO IRQ Mask AND register Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Table 62 Table 62 ...
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... NXP Semiconductors 9. Proprietary Transfer Descriptor (PTD) The standard EHCI data structures as described in Interface Specification for Universal Serial Bus Rev. 1.0” operation that is managed by the hardware state machine. The PTD structures of the SAF1760 are translations of the EHCI data structures that are optimized for the SAF1760 ...
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... NXP Semiconductors 1. Start the PTD memory vertical traversal, considering the skip and LastPTD information, as follows the current PTD is active and not done, perform the transaction. 3. Follow the NextPTD pointer as specified in bits DW4 combined with LastPTD, the LastPTD setting must higher address than the NextPTD specifi ...
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Table 65. High-speed bulk IN and OUT: bit allocation Bit ...
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... NXP Semiconductors Table 66. High-speed bulk IN and OUT: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - — writes NextPTDPointer SW — writes [4:0] DW3 — sets HW — resets — writes — writes — writes SW — writes 59 reserved - — writes HW — ...
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... NXP Semiconductors Table 66. High-speed bulk IN and OUT: bit description Bit Symbol Access Cerr[1:0] HW — writes SW — writes NakCnt[3:0] HW — writes SW — writes reserved - NrBytes HW — writes Transferred SW — writes [14:0] DW2 reserved - RL[3:0] SW — writes 24 reserved - DataStart SW — writes Address[15: reserved ...
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... NXP Semiconductors Table 66. High-speed bulk IN and OUT: bit description Bit Symbol Access DW0 31 EndPt[0] SW — writes Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets 9.2 High-speed isochronous IN and OUT Table 67 Transfer Descriptor (iTD). ...
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Table 67. High-speed isochronous IN and OUT: bit allocation Bit ...
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... NXP Semiconductors Table 68. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW7 ISOIN_7[11:0] HW — writes ISOIN_6[11:0] HW — writes ISOIN_5[11:4] HW — writes DW6 ISOIN_5[3:0] HW — writes ISOIN_4[11:0] HW — writes ISOIN_3[11:0] HW — writes ISOIN_2[11:8] HW — writes DW5 ISOIN_2[7:0] HW — writes ISOIN_1[11:0] HW — writes ISOIN_0[11:0] HW — ...
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... NXP Semiconductors Table 68. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW3 — sets — writes — writes reserved - NrBytes HW — writes Transferred [14:0] DW2 reserved - DataStart SW — writes Address[15: Frame[7:0] SW — writes DW1 reserved - — writes EPType[1:0] SW — writes Token[1:0] SW — ...
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... NXP Semiconductors Table 68. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW0 31 EndPt[0] SW — writes Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — resets SW — sets 9.3 High-speed interrupt IN and OUT Table 69 Descriptor (pTD). SAF1760_1 ...
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Table 69. High-speed interrupt IN and OUT: bit allocation Bit ...
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... NXP Semiconductors Table 70. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW7 INT_IN_7[11:0] HW — writes INT_IN_6[11:0] HW — writes INT_IN_5[11:4] HW — writes DW6 INT_IN_5[3:0] HW — writes INT_IN_4[11:0] HW — writes INT_IN_3[11:0] HW — writes INT_IN_2[11:8] HW — writes DW5 INT_IN_2[7:0] HW — writes INT_IN_1[11:0] HW — writes ...
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... NXP Semiconductors Table 70. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW3 — writes SW — writes — writes reserved - — writes SW — writes Cerr[1:0] HW — writes SW — writes reserved - NrBytes HW — writes Transferred [14:0] DW2 reserved - DataStart SW — writes Address[15:0] ...
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... NXP Semiconductors Table 70. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW0 31 EndPt[0] SW — writes Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets Table 71. Microframe description b Rate 1 1 SOF 2 2 SOF 3 4 SOF ...
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Table 72. Start and complete split for bulk: bit allocation Bit ...
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... NXP Semiconductors Table 73. Start and complete split for bulk: bit description Bit Symbol DW7 reserved DW6 reserved DW5 reserved DW4 reserved NextPTDPointer[4:0] DW3 reserved Cerr[1: NakCnt[3: reserved NrBytes Transferred[14:0] SAF1760_1 Product data sheet Access Value Description - - - - - - - - - - - - SW — ...
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... NXP Semiconductors Table 73. Start and complete split for bulk: bit description Bit Symbol DW2 reserved RL[3:0] 24 reserved DataStartAddress [15: reserved DW1 HubAddress[6: PortNumber[6: SE[1:0] 47 reserved EPType[1: Token[1: DeviceAddress[6: EndPt[3:1] SAF1760_1 Product data sheet …continued Access Value Description - - - SW — writes - Reload set to 0h, hardware ignores the NakCnt value. ...
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... NXP Semiconductors Table 73. Start and complete split for bulk: bit description Bit Symbol DW0 31 EndPt[ reserved MaximumPacket Length[10: NrBytesToTransfer [14: reserved 0 V Table 74. SE description Bulk Control I/O I/O I/O I/O 9.5 Start and complete split for isochronous Table 75 isochronous Transfer Descriptor (siTD). ...
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Table 75. Start and complete split for isochronous: bit allocation Bit ...
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... NXP Semiconductors Table 76. Start and complete split for isochronous: bit description Bit Symbol Access DW7 reserved - ISO_IN_7[7:0] HW — writes DW6 ISO_IN_6[7:0] HW — writes ISO_IN_5[7:0] HW — writes ISO_IN_4[7:0] HW — writes ISO_IN_3[7:0] HW — writes DW5 ISO_IN_2[7:0] HW — writes ISO_IN_1[7:0] HW — writes ISO_IN_0[7:0] HW — writes ...
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... NXP Semiconductors Table 76. Start and complete split for isochronous: bit description Bit Symbol Access DW3 — sets HW — resets — writes — writes — writes — writes 0 HW — updates 58 reserved - — writes SW — writes reserved - NrBytes HW — writes Transferred[11:0] DW2 ...
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... NXP Semiconductors Table 76. Start and complete split for isochronous: bit description Bit Symbol Access DW0 31 EndPt[0] SW — writes reserved - TT_MPS_Len SW — writes [10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets 9.6 Start and complete split for interrupt Table 77 SAF1760_1 Product data sheet ...
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Table 77. Start and complete split for interrupt: bit allocation Bit ...
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... NXP Semiconductors Table 78. Start and complete split for interrupt: bit description Bit Symbol Access DW7 reserved - INT_IN_7[7:0] HW — writes DW6 INT_IN_6[7:0] HW — writes INT_IN_5[7:0] HW — writes INT_IN_4[7:0] HW — writes INT_IN_3[7:0] HW — writes DW5 INT_IN_2[7:0] HW — writes INT_IN_1[7:0] HW — writes INT_IN_0[7:0] HW — writes ...
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... NXP Semiconductors Table 78. Start and complete split for interrupt: bit description Bit Symbol Access SA[7:0] SW — writes (0 HW — writes (1 After processing DW3 — sets HW — resets — writes — writes — writes — writes 0 HW — updates 58 reserved - — writes SW — ...
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... NXP Semiconductors Table 78. Start and complete split for interrupt: bit description Bit Symbol Access — writes EPType[1:0] SW — writes Token[1:0] SW — writes DeviceAddress SW — writes [6: EndPt[3:1] SW — writes DW0 31 EndPt[0] SW — writes reserved - MaxPacketLength SW — writes [10: NrBytesTo SW — writes Transfer[14: reserved ...
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... NXP Semiconductors 10. Power consumption Table 81. Number of ports working One port working (high-speed) V CC(5V0) V CC(5V0) V CC(5V0) V CC(5V0) Two ports working (high-speed) V CC(5V0) V CC(5V0) V CC(5V0) V CC(5V0) Three ports working (high-speed) V CC(5V0) V CC(5V0) V CC(5V0) V CC(5V0) The idle operating current, I initialized and without any devices connected mA. The additional current consumption on I devices ...
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... NXP Semiconductors 11. Limiting values Table 82. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage CC(I/O) V supply voltage (5.0 V) CC(5V0) V electrostatic discharge voltage ESD T storage temperature stg [1] Class 2 according to JEDEC JESD22-A114 . [2] Class III following JEDEC JESD22-C101 . ...
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... NXP Semiconductors 13. Static characteristics Table 84. Static characteristics: digital pins Digital pins: A[17:1], DATA[31:0], CS_N, RD_N, WR_N, DACK, DREQ, IRQ, RESET_N, SUSPEND/WAKEUP_N, CLKIN, OC1_N, OC2_N, OC3_N. OC1_N, OC2_N and OC3_N are used as digital overcurrent pins; T Symbol Parameter 1.95 V CC(I/O) V HIGH-level input voltage ...
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... NXP Semiconductors Table 88. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3 1. 3 +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Input levels for high-speed V high-speed squelch detection HSSQ threshold voltage (differential signal amplitude) V high-speed disconnect detection HSDSC ...
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... NXP Semiconductors 14. Dynamic characteristics Table 89. Dynamic characteristics: system clock timing +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Crystal oscillator f clock frequency clk External clock input t external clock jitter J duty cycle V input voltage on pin XTAL1 i(XTAL1) t rise time r t fall time ...
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... NXP Semiconductors Table 92. Dynamic characteristics: full-speed source electrical characteristics +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Driver characteristics t rise time FR t fall time FF t differential rise and fall time FRFM matching Data timing: see Figure 13 t source jitter for differential ...
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... NXP Semiconductors 14.1 PIO timing 14.1.1 Register or memory write Fig 14. Register or memory write Table 94 +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t h11 t h21 t h31 t w11 t su11 t su21 t su31 3.6 V CC(I/O) t h11 t h21 t h31 t w11 t su11 t su21 t su31 ...
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... NXP Semiconductors 14.1.2 Register read Fig 15. Register read Table 95 +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t su12 t su22 t w12 t d12 t d22 3.6 V CC(I/O) t su12 t su22 t w12 t d12 t d22 14.1.3 Register access CS_N WR_N RD_N Fig 16. Register access ...
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... NXP Semiconductors Table 96 +85 C; unless otherwise specified. amb Symbol t WHRL t RHRL t RHWL t WHWL [1] For EHCI operational registers, minimum value is 195 ns. 14.1.4 Memory read A[17:1] DATA CS_N WR_N RD_N Fig 17. Memory read Table 97 +85 C; unless otherwise specified. amb Symbol 1.95 V ...
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... NXP Semiconductors Table 97 +85 C; unless otherwise specified. amb Symbol t d23 t w13 t su13 t su23 14.2 DMA timing In the following sections: • Polarity of DACK is active HIGH • Polarity of DREQ is active HIGH. 14.2.1 Single cycle: DMA read Fig 18. DMA read (single cycle) Table 98. ...
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... NXP Semiconductors Table 98 +85 C; unless otherwise specified. amb Symbol t w14 t a34 t a44 t h14 14.2.2 Single cycle: DMA write Fig 19. DMA write (single cycle) Table 99 +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) t a15 t a25 t h15 t h25 t su15 ...
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... NXP Semiconductors 14.2.3 Multi-cycle: DMA read Fig 20. DMA read (multi-cycle burst) Table 100. DMA read (multi-cycle burst +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) t a16 t a26 t d16 t w16 T cy16 t a36 t a46 t h16 3.6 V CC(I/O) t a16 t a26 ...
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... NXP Semiconductors 14.2.4 Multi-cycle: DMA write Fig 21. DMA write (multi-cycle burst) Table 101. DMA write (multi-cycle burst +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) T cy17 t su17 t h17 t a17 t a27 t a37 t h27 t a47 t w17 t a57 3.6 V CC(I/O) ...
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... NXP Semiconductors 15. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 102 103 pin 1 index 128 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Appendix 17.1 Errata added on 2009-04-23 17.1.1 Problem description When the SAF1760 is programmed to perform infinite retries on Not Acknowledged (NAK) IN tokens, the SAF1760 does not generate the retry IN tokens on its own ...
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... NXP Semiconductors 17.1.3.2 Hardware retry mechanism Set program register RL = 0000b, NakCnt = 0000b and Cerr = 10b. In this case, interrupt will not be generated for NAKs and hardware will retry indefinitely, until the device responds with a data or an ACK. 17.2 Errata added on 2009-04-23 17 ...
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... NXP Semiconductors • During testing observed that the problem always occurs on the port on which the device was last attached. 17.3.2 Implication The implication will be serious if the device is getting disconnected during the data transfer. 17.3.3 Workaround The software workaround will check if a port has suddenly been disabled (Port Enable bit cleared) when a device is still connected to the port ...
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... NXP Semiconductors 17.3.3.2 Condition 2 Condition 2 refers to the condition when a HALT occurs during PTD processing without other bus errors (that is, babble, transaction error). To determine and resolve the problematic condition, the following steps are taken: • Check the completion status once a PTD scheduled towards a full-speed or low-speed device and connected through the internal hub is completed. • ...
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... NXP Semiconductors 18. Abbreviations Table 104. Abbreviations Acronym ACK ASIC ASYNC ATL ATX BCD CPU CS DSC DMA DW EHCI EMI EOP EOT ESR FIFO FLS GPIO IEC INT I/O IRQ ISO ISR iTD ITL LS NAK NYET OC OHCI PCI PDA SAF1760_1 Product data sheet ...
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... NXP Semiconductors Table 104. Abbreviations Acronym PID PIE PIO PLL PMOS POR PORP PP PPC pTD PTD RAM RISC R/S R/W SE0 SE1 siTD SOF SRAM UHCI USB XOSC [1] Letter X became a synonym for “crystal”. 19. Glossary Bulk transfer — One of the four USB transfer types aperiodic, large burst communication, typically used for a transfer, which works with any available bandwidth ...
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... NXP Semiconductors 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 21. Revision history Table 105. Revision history Document ID Release date SAF1760_1 20091109 SAF1760_1 Product data sheet Embedded Hi-Speed USB host controller ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3. Port connection scenarios . . . . . . . . . . . . . . . .14 Table 4. Memory address . . . . . . . . . . . . . . . . . . . . . . .16 Table 5. Using the IRQ Mask AND or IRQ Mask OR registers . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 6. Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 7. Pin status in hybrid mode . . . . . . . . . . . . . . . .26 Table 8. Register overview . . . . . . . . . . . . . . . . . . . . . .28 Table 9. CAPLENGTH - Capability Length register (address 0000h) bit description ...
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... NXP Semiconductors Table 50. DMA Start Address register (address 0344h) bit description . . . . . . . . . . . .47 Table 51. Power-Down Control register (address 0354h) bit allocation . . . . . . . . . . . . .48 Table 52. Power-Down Control register (address 0354h) bit description . . . . . . . . . . . .48 Table 53. Port 1 Control register (address 0374h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 54. Port 1 Control register (address 0374h) bit description ...
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... NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration (LQFP128); top view . . . . . . . . .5 Fig 3. Internal hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Fig 4. SAF1760 clock scheme . . . . . . . . . . . . . . . . . . . .13 Fig 5. Memory segmentation and access block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Fig 6. Adjusting analog overcurrent detection limit (optional .24 Fig 7. SAF1760 power supply connection . . . . . . . . . . .25 Fig 8. Most commonly used power supply connection .25 Fig 9 ...
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... NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 Examples of a multitude of possible applications Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . 12 7.1 SAF1760 internal architecture: advanced NXP slave host controller and hub . . . . . . . . . 12 7 ...
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... NXP Semiconductors 14.2 DMA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14.2.1 Single cycle: DMA read . . . . . . . . . . . . . . . . . 91 14.2.2 Single cycle: DMA write . . . . . . . . . . . . . . . . . 92 14.2.3 Multi-cycle: DMA read 14.2.4 Multi-cycle: DMA write . . . . . . . . . . . . . . . . . . 94 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 95 16 Soldering of SMD packages . . . . . . . . . . . . . . 96 16.1 Introduction to soldering . . . . . . . . . . . . . . . . . 96 16.2 Wave and reflow soldering . . . . . . . . . . . . . . . 96 16.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 96 16.4 Refl ...