SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 45

• Manufacturer Part Number: SAF1760BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1760BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 44.
Table 45.
[1]
Table 46.
SAF1760_1
Product data sheet
Bit
31 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 18
17 to 16
15 to 0
The reserved bits should always be written with the reset value.
Symbol
-
MEM_BANK_
SEL[1:0]
START_ADDR_
MEM_
READ[15:0]
ATL Done Timeout register (address 0338h) bit description
Memory register (address 033Ch) bit allocation
Memory register (address 033Ch) bit description
Symbol
ATL_DONE_
TIMEOUT[31:0]
8.3.7 ATL Done Timeout register
8.3.8 Memory register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
The bit description of the ATL Done Timeout register is given in
The Memory register contains the base memory read address and the respective bank.
This register needs to be set only before a first memory read cycle. Once written, the
address will be latched for the bank and will be incremented for every read of that bank,
until a new address for that bank is written to change the address pointer.
The bit description of the register is given in
Description
reserved
Memory Bank Select: Up to four memory banks can be selected. For details on internal
memory read description, see
data transfers only.
Start Address for Memory Read Cycles: The start address for a series of memory read
cycles at incremental addresses in a contiguous space. Applicable to PIO mode memory read
data transfers only.
Access
R/W
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Value
0000 0000h
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 9 November 2009
reserved
START_ADDR_MEM_READ[15:8]
START_ADDR_MEM_READ[7:0]
Description
ATL Done Timeout: This register determines the ATL done
time-out interrupt. This register defines the time-out in
milliseconds after which the SAF1760 asserts the INT line, if
enabled. It is applicable to ATL done PTDs only.
[1]
R/W
R/W
R/W
R/W
Section
28
20
12
0
0
0
4
0
reserved
7.3.1. Applicable to PIO mode memory read or write
[1]
R/W
R/W
R/W
R/W
Table
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
45.
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
Table
MEM_BANK_SEL[1:0]
R/W
R/W
R/W
R/W
25
17
44.
0
0
9
0
1
0
SAF1760
© NXP B.V. 2009. All rights reserved.
R/W
R/W
R/W
R/W
45 of 110
24
16
0
0
8
0
0
0