SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 46

• Manufacturer Part Number: SAF1760BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1760BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 47.
[1]
Table 48.
SAF1760_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 24
23 to 16
15 to 0
The reserved bits should always be written with the reset value.
Symbol
MIN_WIDTH
[7:0]
-
NO_OF_CLK
[15:0]
Edge Interrupt Count register (address 0340h) bit allocation
Edge Interrupt Count register (address 0340h) bit description
8.3.9 Edge Interrupt Count register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 47
Description
Minimum Width: Indicates the minimum width between two edge interrupts in SOFs
(1 SOF = 125 s). This is not valid for level interrupts. A count of zero means that interrupts
occur as and when an event occurs.
reserved
Number of Clocks: Count in number of clocks that the edge interrupt must be kept asserted
on the interface. The default value is 000Fh. Thus, 15 cycles of 30 MHz clock will make the
default IRQ pulse width approximately 500 ns.
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
shows the bit allocation of the register.
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 9 November 2009
NO_OF_CLK[15:8]
R/W
R/W
R/W
R/W
NO_OF_CLK[7:0]
MIN_WIDTH[7:0]
28
20
12
0
0
0
4
0
reserved
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
1
Embedded Hi-Speed USB host controller
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
1
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
1
SAF1760
© NXP B.V. 2009. All rights reserved.
R/W
R/W
R/W
R/W
46 of 110
24
16
0
0
8
0
0
1