SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 13

• Manufacturer Part Number: SAF1760BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1760BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1760_1
Product data sheet
7.1.1 Internal clock scheme and port selection
The SAF1760 has three ports.
Figure 4
enabled by software, if only port 1 or port 3 is used. No port needs to be disabled by
external pull-up resistors, if not used. The DP and DM of the unused ports need not be
externally pulled HIGH because there are internal pull-down resistors on each port that
are enabled by default.
Table 3
Fig 3.
Fig 4.
lists the various port connection scenarios.
shows that the host clock is derived from port 2. Port 2 does not need to be
Internal hub
SAF1760 clock scheme
Rev. 01 — 9 November 2009
XOSC
PORT1
PLL 12 MHz IN
Figure 4
AND POLLING USING
INTERNAL HUB (TT)
ENUMERATION
ACTUAL PTDs
ROOT HUB
PORTSC1
PORT2
EHCI
PORT 2
PORT 3
PORT 1
shows the internal clock scheme of the SAF1760.
ATX
ATX
ATX
Embedded Hi-Speed USB host controller
host clock:
48 MHz,
30 MHz,
60 MHz
PORT3
DIGITAL CORE
EXTERNAL
PORTS
CORE
HOST
004aaa513
004aaa535
SAF1760
© NXP B.V. 2009. All rights reserved.
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