SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 109

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SAF1760BE/V1,557

Manufacturer Part Number
SAF1760BE/V1,557
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAF1760BE/V1,557

Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAF1760BE/V1,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
26. Contents
1
2
3
3.1
4
5
6
6.1
6.2
7
7.1
7.1.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
7.6
7.7
7.8
7.8.1
7.9
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
SAF1760_1
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . 12
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Examples of a multitude of possible
applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
SAF1760 internal architecture: advanced
NXP slave host controller and hub . . . . . . . . . 12
Internal clock scheme and port selection . . . . 13
Host controller buffer memory block . . . . . . . . 14
General considerations. . . . . . . . . . . . . . . . . . 14
Structure of the SAF1760 host controller
memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Accessing the SAF1760 host controller
memory: PIO and DMA . . . . . . . . . . . . . . . . . 17
PIO mode access, memory read cycle . . . . . . 17
PIO mode access, memory write cycle . . . . . 18
PIO mode access, register read cycle . . . . . . 18
PIO mode access, register write cycle . . . . . . 18
DMA mode, read and write operations . . . . . . 18
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Phase-Locked Loop (PLL) clock multiplier . . . 22
Power management . . . . . . . . . . . . . . . . . . . . 22
Overcurrent detection . . . . . . . . . . . . . . . . . . . 23
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 25
Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 27
EHCI capability registers . . . . . . . . . . . . . . . . 29
CAPLENGTH register. . . . . . . . . . . . . . . . . . . 29
HCIVERSION register . . . . . . . . . . . . . . . . . . 29
HCSPARAMS register . . . . . . . . . . . . . . . . . . 30
HCCPARAMS register . . . . . . . . . . . . . . . . . . 31
EHCI operational registers . . . . . . . . . . . . . . . 32
USBCMD register . . . . . . . . . . . . . . . . . . . . . . 32
USBSTS register . . . . . . . . . . . . . . . . . . . . . . 33
USBINTR register . . . . . . . . . . . . . . . . . . . . . . 34
FRINDEX register . . . . . . . . . . . . . . . . . . . . . . 34
CONFIGFLAG register . . . . . . . . . . . . . . . . . . 35
PORTSC1 register . . . . . . . . . . . . . . . . . . . . . 35
ISO PTD Done Map register. . . . . . . . . . . . . . 37
Rev. 01 — 9 November 2009
8.2.8
8.2.9
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
8.2.15
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
9
9.1
9.2
9.3
9.4
9.5
9.6
10
11
12
13
14
14.1
14.1.1
14.1.2
14.1.3
14.1.4
Proprietary Transfer Descriptor (PTD). . . . . . 56
Power consumption . . . . . . . . . . . . . . . . . . . . 82
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 83
Recommended operating conditions . . . . . . 83
Static characteristics . . . . . . . . . . . . . . . . . . . 84
Dynamic characteristics . . . . . . . . . . . . . . . . . 86
ISO PTD Skip Map register . . . . . . . . . . . . . . 37
ISO PTD Last PTD register . . . . . . . . . . . . . . 37
INT PTD Done Map register. . . . . . . . . . . . . . 38
INT PTD Skip Map register . . . . . . . . . . . . . . 38
INT PTD Last PTD register . . . . . . . . . . . . . . 38
ATL PTD Done Map register . . . . . . . . . . . . . 39
ATL PTD Skip Map register . . . . . . . . . . . . . . 39
ATL PTD Last PTD register . . . . . . . . . . . . . . 39
Configuration registers . . . . . . . . . . . . . . . . . . 40
HW Mode Control register . . . . . . . . . . . . . . . 40
Chip ID register . . . . . . . . . . . . . . . . . . . . . . . 41
Scratch register . . . . . . . . . . . . . . . . . . . . . . . 41
SW Reset register . . . . . . . . . . . . . . . . . . . . . 42
DMA Configuration register . . . . . . . . . . . . . . 43
Buffer Status register . . . . . . . . . . . . . . . . . . . 44
ATL Done Timeout register . . . . . . . . . . . . . . 45
Memory register . . . . . . . . . . . . . . . . . . . . . . . 45
Edge Interrupt Count register. . . . . . . . . . . . . 46
DMA Start Address register . . . . . . . . . . . . . . 47
Power-Down Control register . . . . . . . . . . . . . 48
Port 1 Control register . . . . . . . . . . . . . . . . . . 50
Interrupt registers . . . . . . . . . . . . . . . . . . . . . . 51
Interrupt register. . . . . . . . . . . . . . . . . . . . . . . 51
Interrupt Enable register. . . . . . . . . . . . . . . . . 53
ISO IRQ Mask OR register. . . . . . . . . . . . . . . 54
INT IRQ Mask OR register . . . . . . . . . . . . . . . 54
ATL IRQ Mask OR register. . . . . . . . . . . . . . . 54
ISO IRQ Mask AND register . . . . . . . . . . . . . 55
INT IRQ Mask AND register. . . . . . . . . . . . . . 55
ATL IRQ Mask AND register . . . . . . . . . . . . . 55
High-speed bulk IN and OUT . . . . . . . . . . . . . 57
High-speed isochronous IN and OUT . . . . . . 61
High-speed interrupt IN and OUT . . . . . . . . . 65
Start and complete split for bulk . . . . . . . . . . . 69
Start and complete split for isochronous . . . . 73
Start and complete split for interrupt . . . . . . . 77
PIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Register or memory write . . . . . . . . . . . . . . . . 88
Register read . . . . . . . . . . . . . . . . . . . . . . . . . 89
Register access . . . . . . . . . . . . . . . . . . . . . . . 89
Memory read . . . . . . . . . . . . . . . . . . . . . . . . . 90
Embedded Hi-Speed USB host controller
SAF1760
© NXP B.V. 2009. All rights reserved.
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