SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 55

• Manufacturer Part Number: SAF1760BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1760BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 61.
Table 62.
Table 63.
Table 64.
SAF1760_1
Product data sheet
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0
Symbol
ATL_IRQ_MASK
_OR[31:0]
Symbol
ISO_IRQ_MASK
_AND[31:0]
Symbol
INT_IRQ_MASK
_AND[31:0]
Symbol
ATL_IRQ_MASK
_AND[31:0]
ATL IRQ Mask OR register (address 0320h) bit description
ISO IRQ Mask AND register (address 0324h) bit description
INT IRQ Mask AND register (address 0328h) bit description
ATL IRQ Mask AND register (address 032Ch) bit description
8.4.6 ISO IRQ Mask AND register
8.4.7 INT IRQ Mask AND register
8.4.8 ATL IRQ Mask AND register
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Table 62
Each bit of this register (see
and is a hardware IRQ mask for each PTD done map. For details, see
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Table 64
Access
R/W
Access Value
R/W
Access
R/W
Access
R/W
provides the bit description of the register.
shows the bit description of the register.
0000 0000h
Value
0000 0000h INT IRQ Mask AND: Represents a direct map for INT PTDs 31 to 0.
Value
0000 0000h ISO IRQ Mask AND: Represents a direct map for ISO PTDs 31 to 0.
Value
0000 0000h ATL IRQ Mask AND: Represents a direct map for ATL PTDs 31 to 0.
Rev. 01 — 9 November 2009
Description
ATL IRQ Mask OR: Represents a direct map for ATL PTDs 31 to 0.
0 — No OR condition defined between the ATL PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain OR condition.
Description
0 — No AND condition defined between ISO PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain AND condition between the 32 INT PTDs.
Description
0 — No OR condition defined between INT PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain AND condition between the 32 INT PTDs.
Description
0 — No OR condition defined between ATL PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain AND condition between the 32 ATL PTDs.
Table
63) corresponds to one of the 32 INT PTDs defined,
Embedded Hi-Speed USB host controller
Section
Section
7.4.
7.4.
SAF1760
Section
© NXP B.V. 2009. All rights reserved.
7.4.
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