SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 107

• Manufacturer Part Number: SAF1760BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1760BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 50. DMA Start Address register
Table 51. Power-Down Control register
Table 52. Power-Down Control register
Table 53. Port 1 Control register (address 0374h)
Table 54. Port 1 Control register (address 0374h)
Table 55. Interrupt register (address 0310h) bit
Table 56. Interrupt register (address 0310h) bit
Table 57. Interrupt Enable register (address 0314h)
Table 58. Interrupt Enable register (address 0314h)
Table 59. ISO IRQ Mask OR register (address 0318h)
Table 60. INT IRQ Mask OR register (address 031Ch)
Table 61. ATL IRQ Mask OR register (address 0320h)
Table 62. ISO IRQ Mask AND register (address 0324h)
Table 63. INT IRQ Mask AND register (address 0328h)
Table 64. ATL IRQ Mask AND register (address 032Ch)
Table 65. High-speed bulk IN and OUT: bit allocation . . .58
Table 66. High-speed bulk IN and OUT: bit description .59
Table 67. High-speed isochronous IN and OUT: bit
Table 68. High-speed isochronous IN and OUT: bit
Table 69. High-speed interrupt IN and OUT:
Table 70. High-speed interrupt IN and OUT:
Table 71. Microframe description . . . . . . . . . . . . . . . . . .69
Table 72. Start and complete split for bulk:
Table 73. Start and complete split for bulk:
Table 74. SE description . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 75. Start and complete split for isochronous:
Table 76. Start and complete split for isochronous:
Table 77. Start and complete split for interrupt:
Table 78. Start and complete split for interrupt:
Table 79. Microframe description . . . . . . . . . . . . . . . . . .81
Table 80. SE description . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 81. Power consumption . . . . . . . . . . . . . . . . . . . . .82
Table 82. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .83
SAF1760_1
Product data sheet
(address 0344h) bit description . . . . . . . . . . . .47
(address 0354h) bit allocation . . . . . . . . . . . . .48
(address 0354h) bit description . . . . . . . . . . . .48
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .50
bit description . . . . . . . . . . . . . . . . . . . . . . . . .50
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .53
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .66
bit description . . . . . . . . . . . . . . . . . . . . . . . . .67
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .70
bit description . . . . . . . . . . . . . . . . . . . . . . . . .71
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .74
bit description . . . . . . . . . . . . . . . . . . . . . . . . .75
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .78
bit description . . . . . . . . . . . . . . . . . . . . . . . . .79
Rev. 01 — 9 November 2009
Table 83. Recommended operating conditions . . . . . . . . 83
Table 84. Static characteristics: digital pins . . . . . . . . . . 84
Table 85. Static characteristics: PSW1_N, PSW2_N,
Table 86. Static characteristics: POR . . . . . . . . . . . . . . . 84
Table 87. Static characteristics: REF5V . . . . . . . . . . . . . 84
Table 88. Static characteristics: USB interface block
Table 89. Dynamic characteristics: system
Table 90. Dynamic characteristics: CPU interface
Table 91. Dynamic characteristics: high-speed
Table 92. Dynamic characteristics: full-speed
Table 93. Dynamic characteristics: low-speed
Table 94. Register or memory write . . . . . . . . . . . . . . . . 88
Table 95. Register read . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 96. Register access . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 97. Memory read . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 98. DMA read (single cycle) . . . . . . . . . . . . . . . . . 91
Table 99. DMA write (single cycle) . . . . . . . . . . . . . . . . . 92
Table 100.DMA read (multi-cycle burst) . . . . . . . . . . . . . . 93
Table 101.DMA write (multi-cycle burst) . . . . . . . . . . . . . 94
Table 102.SnPb eutectic process (from J-STD-020C) . . . 97
Table 103.Lead-free process (from J-STD-020C) . . . . . . 97
Table 104.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 105.Revision history . . . . . . . . . . . . . . . . . . . . . . . 104
PSW3_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
(pins DM1 to DM3 and DP1 to DP3) . . . . . . . . 85
clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
source electrical characteristics . . . . . . . . . . . 86
source electrical characteristics . . . . . . . . . . . 87
source electrical characteristics . . . . . . . . . . . 87
Embedded Hi-Speed USB host controller
SAF1760
© NXP B.V. 2009. All rights reserved.
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