SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 49

• Manufacturer Part Number: SAF1760BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1760BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 52.
[1]
SAF1760_1
Product data sheet
Bit
10
9 to 6
5
4
3
2
1
0
[1]
For a 32-bit operation, the default wake-up counter value is 10 s. For a 16-bit operation, the wake-up counter value is 50 ms. In the
16-bit operation, read and write back the same value on initialization.
Symbol
VBATDET_PW
R
-
BIASEN
VREG_ON
OC3_PWR
OC2_PWR
OC1_PWR
HC_CLK_EN
Power-Down Control register (address 0354h) bit description
Description
V
0 — V
1 — V
reserved; write reset value
Bias Circuits Powered: Controls the power to internal bias circuits.
0 — Internal bias circuits are not powered in suspend.
1 — Internal bias circuits are powered in suspend.
V
SAF1760
0 — Internal regulators are normally powered in suspend.
1 — Internal regulators switch to low power mode (in suspend mode).
OC3_N Powered: Controls the powering of the overcurrent detection circuitry for port 3.
0 — Overcurrent detection is powered-on or enabled during suspend.
1 — Overcurrent detection is powered-off or disabled during suspend.
This may be useful when connecting a faulty device while the system is in standby.
OC2_N Powered: Controls the powering of the overcurrent detection circuitry for port 2.
0 — Overcurrent detection is powered-on or enabled during suspend.
1 — Overcurrent detection is powered-off or disabled during suspend.
This may be useful when connecting a faulty device while the system is in standby.
OC1_N Powered: Controls the powering of the overcurrent detection circuitry for port 1.
0 — Overcurrent detection is powered-on or enabled during suspend.
1 — Overcurrent detection is powered-off or disabled during suspend.
This may be useful when connecting a faulty device while the system is in standby.
Host Controller Clock Enabled: Controls internal clocks during suspend.
0 — Clocks are disabled during suspend. This is the default value. Only the LazyClock of
100 kHz
suspend, CLKREADY IRQ will be generated when all clocks are running stable.
1 — All clocks are enabled even in suspend.
BAT
REG
Detector Powered: Controls the power to the V
Powered: Enables or disables the internal 3.3 V and 1.8 V regulators when the
BAT
BAT
detector is powered or enabled in suspend.
detector is not powered or disabled in suspend.
40 % will be left running in suspend if this bit is logic 0. If clocks are stopped during
is in suspend.
Rev. 01 — 9 November 2009
Embedded Hi-Speed USB host controller
…continued
BAT
detector.
SAF1760
© NXP B.V. 2009. All rights reserved.
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