SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 40

• Manufacturer Part Number: SAF1760BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1760BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 34.
[1]
Table 35.
SAF1760_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31
30 to 16
15
14 to 9
8
7
6
The reserved bits should always be written with the reset value.
Symbol
ALL_ATX_RESET
-
ANA_DIGI_OC
-
DATA_BUS_WIDTH
-
DACK_POL
HW Mode Control - Hardware Mode Control register (address 0300h) bit allocation
HW Mode Control - Hardware Mode Control register (address 0300h) bit description
ANA_DIGI_
ALL_ATX_
reserved
8.3.1 HW Mode Control register
RESET
R/W
R/W
R/W
R/W
8.3 Configuration registers
OC
31
23
15
0
0
0
7
0
Table 34
DACK_
POL
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Description
All ATX Reset: For debugging purposes (not used normally).
1 — Enable reset, then write back logic 0
0 — No reset
reserved; write logic 0
Analog Digital Overcurrent: This bit selects analog or digital overcurrent detection on
pins OC1_N, OC2_N and OC3_N.
0 — Digital overcurrent
1 — Analog overcurrent
reserved; write logic 0
Data Bus Width:
0 — Defines a 16-bit data bus width
1 — Sets a 32-bit data bus width
reserved; write logic 0
DACK Polarity:
1 — Indicates that the DACK input is active HIGH
0 — Indicates active LOW
shows the bit allocation of the register.
DREQ_
R/W
R/W
R/W
POL
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 9 November 2009
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
reserved
reserved
[1]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
[1]
INTR_POL
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
LEVEL
INTR_
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
SAF1760
© NXP B.V. 2009. All rights reserved.
DATA_BUS
GLOBAL_
INTR_EN
_WIDTH
R/W
R/W
R/W
R/W
40 of 110
24
16
0
0
8
1
0
0