SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 48

• Manufacturer Part Number: SAF1760BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1760BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 51.
[1]
Table 52.
SAF1760_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 16
15 to 13
12
11
[1]
The reserved bits should always be written with the reset value.
Symbol
CLK_OFF_
COUNTER
[15:0]
-
PORT3_PD
PORT2_PD
Power-Down Control register (address 0354h) bit allocation
Power-Down Control register (address 0354h) bit description
8.3.11 Power-Down Control register
R/W
R/W
R/W
R/W
15
31
23
0
0
1
7
1
reserved
This register is used to turn off power to the internal blocks of the SAF1760 to obtain
maximum power savings.
reserved
Description
Clock Off Counter: Determines the wake-up status duration after any wake-up event before
the SAF1760 goes back into suspend mode. This time-out is applicable only if, during the
given interval, the host controller is not programmed back to the normal functionality.
03E8h — The default value. It determines the default wake-up interval of 10 ms. A value of
zero implies that the host controller never wakes up on any of the events. This may be useful
when using the SAF1760 as a peripheral to save power by permanently programming the host
controller in suspend.
FFFFh — The maximum value. It determines a maximum wake-up time of 500 ms.
The setting of this register is based on the 100 kHz
of 10 s period.
Remark: In 16-bit mode, the default value is 17E8h. A write operation to these bits with any
value fixes the clock off counter at 1400h. This value is equivalent to a fixed wake-up time of
50 ms.
reserved
Port 3 Pull-Down: Controls port 3 pull-down resistors.
0 — Port 3 internal pull-down resistors are not connected.
1 — Port 3 internal pull-down resistors are connected.
Port 2 Pull-Down: Controls port 2 pull-down resistors.
0 — Port 2 internal pull-down resistors are not connected.
1 — Port 2 internal pull-down resistors are connected.
[1]
R/W
R/W
R/W
R/W
14
30
22
0
0
1
6
0
[1]
BIASEN
R/W
R/W
R/W
R/W
13
29
21
0
5
1
0
1
Rev. 01 — 9 November 2009
Table 51
CLK_OFF_COUNTER[15:8]
CLK_OFF_COUNTER[7:0]
VREG_ON
PORT3_
R/W
R/W
PD
R/W
R/W
12
4
0
1
28
20
0
0
shows the bit allocation of the register.
OC3_PWR OC2_PWR OC1_PWR
PORT2_
R/W
R/W
PD
11
R/W
R/W
1
3
0
27
19
0
1
Embedded Hi-Speed USB host controller
40 % LazyClock frequency. It is a multiple
VBATDET_
PWR
R/W
R/W
10
2
0
R/W
R/W
0
26
18
0
0
R/W
1
0
R/W
R/W
R/W
25
17
9
1
1
0
SAF1760
© NXP B.V. 2009. All rights reserved.
reserved
HC_CLK_EN
[1]
R/W
R/W
R/W
R/W
0
0
48 of 110
24
16
1
0
8
1