SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 22

• Manufacturer Part Number: SAF1760BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1760BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1760_1
Product data sheet
7.5 Phase-Locked Loop (PLL) clock multiplier
7.6 Power management
Table 5.
The internal PLL requires a 12 MHz input, which can be a 12 MHz crystal or a 12 MHz
clock already existing in the system with a precision better than 50
use of a low-cost 12 MHz crystal that also minimizes ElectroMagnetic Interference (EMI).
When an external crystal is used, make sure the CLKIN pin is connected to V
The PLL block generates all the main internal clocks required for normal functionality of
various blocks: 30 MHz, 48 MHz and 60 MHz.
No external components are required for the PLL operation.
The SAF1760 implements a flexible power management scheme, allowing various power
saving stages.
The usual powering scheme implies programming EHCI registers and the internal
Hi-Speed USB (USB 2.0) hub in the same way it is done in the case of a PCI Hi-Speed
USB host controller with a Hi-Speed USB hub attached.
When the SAF1760 is in suspend mode, the main internal clocks will be stopped to
ensure minimum power consumption. An internal LazyClock of 100 kHz
continue running. This allows initiating a resume on one of these events:
The SUSPEND/WAKEUP_N pin is a bidirectional pin. This pin must be connected to the
GPIO pins of a processor.
The wake up state can be verified by reading the LOW level of this pin. If the level is HIGH,
it means that the SAF1760 is in the suspend state.
The SUSPEND/WAKEUP_N pin requires a pull-up because in the SAF1760 suspended
state the pin becomes 3-state and can be pulled down, driving it externally by switching
the processors GPIO line to output mode to generate the SAF1760 wake-up.
PTD
1
2
3
4
5
6
7
8
9
•
•
•
External USB device connect or disconnect
CS_N signal asserted when the SAF1760 is accessed
Driving the SUSPEND/WAKEUP_N pin to a LOW level
AND register
1
1
0
1
0
0
0
0
0
Using the IRQ Mask AND or IRQ Mask OR registers
Rev. 01 — 9 November 2009
OR register
0
0
0
0
0
0
1
1
1
Time
1 ms
-
-
3 ms
-
-
5 ms
6 ms
7 ms
Embedded Hi-Speed USB host controller
PTD done
1
1
-
1
-
-
1
1
1
IRQ
-
-
-
active because of AND
-
-
active because of OR
active because of OR
active because of OR
10
SAF1760
© NXP B.V. 2009. All rights reserved.
6
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