ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 166

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
3.10: DMAQS Enqueue DMA Descriptor Primitive
This register enqueues a DMA descriptor chain to the corresponding DMA queue. The write data is the
address of the descriptor chain that describes the DMA transfers. The low six bits contain a count of the num-
ber of DMA descriptors in this chain. After the DMA descriptors are enqueued by writing to this register, the
chain of descriptors is fetched from system memory and the DMA transfers described by the chain of descrip-
tors are performed. In 32 bit addressing mode, the low-order 32 bits of the register are written, and the
high-order 32 bits are reset when the register is loaded.
Length
Type
Address
Power on Value
Restrictions
3.11: DMAQS Source Address Register
This register is used to set and keep track of the Source Address during a DMA transfer. This is the source for
the current DMA transfer. A bit in the Transfer Count and Flag Register determines whether the source
address is internal to the IBM3206K0424 or is a system address. In 32-bit addressing mode, the low-order 32
bits of the register are written, and the high-order 32 bits are reset when the register is loaded.
Length
Type
Address
Power on Value
Restrictions
DMA QUEUES (DMAQS)
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64 bits
Write
Queue 0
Queue 1
Queue 2
Queue 0
Queue 1
Queue 2
None
64 bits
Read/Write
Queue 0
Queue 1
Queue 2
X’0000000000000000’
None
XXXX 0620
XXXX 06A0
XXXX 0720
X’00000000000000000’
X’00000000’
X’00000000’
XXXX 0638
XXXX 06B8
XXXX 0738
pnr25.chapt04.01
August 14, 2000
Preliminary