ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 541

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
Event Latch Registers
The optional event latch register(s) remember one ore more occurances of events that happen in a chiplet.
This may be considered as a one-bit saturating counter. Each bit in the register corresponds to an event in
the chiplet. Such bits remain high after the event happened until the microprocessor implicitly or explicitly
resets the bit. This is configurable: implicit reset is done by writing a high value to the bit that is to be reset.
Explicit will reset all bits of one register when the register is read. This is a read/write register.
Interrupt Registers
When there are counters, user interrupts, or fatal bits in a chiplet, a MAIN INTERRUPT register will be
present. Bit 0 always is the fatal interrupt bit, which is set as soon as any of the fatal interrupt events occur.
The other bits refer to counters or user interrupt registers to allow easy determination of the interrupt cause.
Each Interrupt register has an interrupt MASK register to enable or disable interrupt. After power on Reset,
interrupts are disabled. The interrupt registers are the same as the event latch registers, with the addition that
when an interrupt register bit is set, and the corresponding mask register bit is set, the interrupt signal to the
GPPINT chiplet is activated. The same mechanism to reset the interrupt register bits is used as for the event
latch registers. The interrupt MASK registers are only changed by the microprocessor. The interrupt and
interrupt mask registers are read/write.
Configuration Registers
These registers are programmed by the microprocessor with setup information, and are read/write. The first
configuration register reserves bit 1 and seven to configure explicit or implicit reset of the event latch registers
and interrupt registers respectively (when such registers are present).
Register Types
F
N
R
I
C
X
S
O
pnr25.chapt06.01
August 14, 2000
Read-On-The-Fly register (auto-generated)
Counter register
Reset register
Interrupt register (auto-generated)
Configuration register
Control or mask register (auto-generated)
Status (event latch) register
Command register
IBM Processor for Network Resources
GPPHandler Architecture
Page 541 of 676
IBM3206K0424