ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 498

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
17.55: PCORE ABR Output Rate Register
This register is the output port of the rate conversion logic. An integer rate was placed in the Integer Input
Register. The logic converts it to an ABR rate and places the result in this register.
Length
Type
DCR Address
Power on Reset value
Restrictions
17.56: PCORE Debug States Control
This register serves as the PCORE control for external debug states. The INTST Debug states control for the
address range desired must be set to select these PCORE state bits. If that is done, then this register acts to
select the four ranges. See bit descriptions below.
Length
Type
Address
Power on Reset value
Restrictions
Processor Core (PCORE)
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Entity State Mux Control 4
31-24
23-16
Bit(s)
15-8
7-0
(Hardware debug)
Entity State Mux Control 4
(Hardware debug)
Entity State Mux Control 3
(Hardware debug)
Entity State Mux Control 2
(Hardware debug)
Entity State Mux Control 1
(Hardware debug)
Name
16 bits
Read
X’20C’
X’00 00’
None
32 bits
Read/Write
XXXX 431C
X’0000 0000’
None
Entity State Mux Control 3
(Hardware debug)
Select of these bits allows internal state machines, counters, etc., to show up on chip
outputs ENSTATE(63 down to 48). Selection encoding is the same as mux 1 control.
Select of these bits allow internal state machines, counters, etc., to show up on chip
outputs ENSTATE(47 down to 32). Selection encoding is the same as mux 1 control.
Select of these bits allow internal state machines, counters, etc., to show up on chip
outputs ENSTATE(31 down to 16). Selection encoding is the same as mux 1 control.
Select of these bits allow internal state machines, counters, etc., to show up on chip
outputs ENSTATE(15 down to 0).
X’00’ Disabled (no transition on outputs)
X’01’ Select 15-0 states
X’40’-X’FF’ Reserved
Entity State Mux Control 2
(Hardware debug)
Description
8
7
Entity State Mux Control 1
6
(Hardware debug)
5
4
pnr25.chapt05.01
August 14, 2000
3
Preliminary
2
1
0