ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 45

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
DRAM Memory Bus Interface Pin Descriptions
pnr25.chapt02.01
August 14, 2000
Quantity
21
21
39
39
4
4
2
2
2
2
2
2
2
2
5
1
5
1
CMSYNRAS(1:0)
CMSYNCAS(1:0)
PMSYNRAS(1:0)
PMSYNCAS(1:0)
PMADDR(20:0)
CMADDR(20:0)
PMDATA(38:0)
CMDATA(38:0)
CMnDQM(3:0)
PMnDQM(3:0)
PMnCS(3:0)
CMnCS(3:0)
PMCLK(4:0)
CMWE(1:0)
CMCLK(4:0)
PMWE(1:0)
Pin Name
PMCLKE
CMCLKE
Input/Output
Input/Output Packet Memory clock enable
Input/Output Control Memory clock enable
Input/Output
Input/Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Packet Memory SRAM chip selects
Control Memory SRAM chip selects
Packet memory DQM lines
Control memory DQM lines
RAS signal for packet synchronous
DRAM
RAS signal for control synchronous
DRAM
CAS signal for packet synchronous
DRAM
CAS signal for control synchronous
DRAM
Packet Memory write enable
Control Memory write enable
Packet Memory clock
Control Memory clock
Address signals to Packet Memory
Address signals to Control Memory
Data signals to and from the Packet
Memory
Data signals to and from the Control
Memory.
Pin Function
PMnCS(3:2) are bank address lines 1 and 0 and
PMnCS(1:0) are the chip selects for the two arrays
when using SDRAM for Packet Memory. When
using SRAM, they are either the four chip selects or
are eight-encoded chip selects and a valid signal.
CMnCS(3:2) are bank address lines 1 and 0 and
CMnCS(1:0) are the chip selects for the two arrays
when using SDRAM for Control Memory. When
using SRAM, they are either the four chip selects or
are eight-encoded chip selects and a valid signal.
PMDQM(3:0) are the DQM lines when using
SDRAM for Packet Memory. They are identical cop-
ies of output enable when using SRAM.
PMDQM(3:2) is just another copy of PMDQM(1:0)
to reduce loading on the nets.
CM0DQM(3:0) are the DQM lines when using
SDRAM for Control Memory. They are identical
copies of output enable when using SRAM.
CMDQM(3:2) is just another copy of CMDQM(1:0)
to reduce loading on the nets.
PMSYNRAS(1:0) are identical copies of the RAS
signal for Packet Memory when using SDRAM.
They are byte enables (3:2) when using SRAM.
CMSYNRAS(1:0) are identical copies of the RAS
signal for Control Memory when using SDRAM.
They are byte enables (3:2) when using SRAM.
PMSYNCAS(1:0) are identical copies of the CAS
signal for Packet Memory when using SDRAM.
They are byte enables (1:0) when using SRAM.
CMSYNCAS(1:0) are identical copies of the CAS
signal for Control Memory when using SDRAM.
They are byte enables (1:0) when using SRAM.
Packet memory write enable.
Control memory write enable.
Clock enable for Packet Memory when using
SDRAM.
There are five copies to minimize loading.
Clock enable output for Control Memory when using
SDRAM.
There are five copies to minimize loading.
IBM Processor for Network Resources
Pin Description
DRAM Memory Bus Interface
IBM3206K0424
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