ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 448

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ibm3206k0424

Manufacturer Part Number
ibm3206k0424
Description
Ibm Processor For Network Resources
Manufacturer
ETC-unknow
Datasheet
IBM3206K0424
IBM Processor for Network Resources
Optional Architecture Extensions
Caches
Memory Management
Interrupt Controller
Debug Support
Interfaces
On-Chip Memory
IBM3206K0424 Registers
PCI Bus
Comet/Pakit Memory
Processor Core (PCORE)
Page 448 of 676
• Programmable boot address (system interrupt vector)
• Interrupt enhancements
• 32-byte cache lines (eight words/line)
• Four-way set associative write back 32k instruction and data caches
• Real Flat Address Mode supported
• Two interrupt levels external to COBRA: normal and critical
• Three-way interrupts
• PowerPC JTAG debugger support (401 RiscWatch)
• 401 debug instructions
• Serial Port Debugger support
• PCI Debug access to JTAG debug facilities
• 96k of on-chip memory
• Can be used simultaneously by instruction and data accesses
• OCM Basic DMA controller provides bulk data moves to/from OCM
• Read/Write access to the IBM3206K0424 register bus
• Some critical registers are mapped to COBRA Core DCR register space
• Read/Write master access to PCI Bus
• Currently no actual streaming/bursting supported
• Pseudo bursting supported (multiple back to back single transfers)
• Interrupt sink
• No arbitration supported (we are not a complete bridge)
• Able to use both memory controllers for both instruction and data accesses
- Individually re-locatable interrupts
- Individually programmable interrupt level (normal/critical)
- From IBM3206K0424 to COBRA
- From COBRA to PCI
- From PCI to COBRA
pnr25.chapt05.01
August 14, 2000
Preliminary

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