ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 429

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
pnr25.chapt05.01
August 14, 2000
Bit(s)
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
Status LED 3 Toggle
Status LED 2 Toggle
Status LED 1 Toggle
Status LED 4 Flashing
Status LED 3 Flashing
Status LED 2 Flashing
Status LED 1 Flashing
Status LED 4 On
Status LED 3 On
Status LED 2 On
Status LED 1 On
+UTP/-STP Interface Select
Disable driving the NP address
over the ENSTATE(47 - 32) pins
Enable Carrier Detect LED
Enable PHY Data Bus
Parity Detection
Enable 16 data bit mode for PHY
reg accesses
Access Internal SONET Framer
register space in memory mapped
mode
PHY Bus Interface Type
Enable Hardware Error to
Disable PHY
Reboot serial/parallel EPROM
Remove Internal SONET Framer
from reset state
Name
When this bit is set, the state of bit 18 of this register will be toggled by repeatedly set-
ting bit 18.
When this bit is set, the state of bit 17 of this register will be toggled by repeatedly set-
ting bit 17.
When this bit is set, the state of bit 16 of this register will be toggled by repeatedly set-
ting bit 16.
When set to ’1’, this bit will flash status indicator LED 4. Bit 19 of the register will over-
ride this bit.
When set to ’1’, this bit will flash status indicator LED 3. Bit 18 of the register will over-
ride this bit.
When set to ’1’, this bit will flash status indicator LED 2. Bit 17 of the register will over-
ride this bit.
When set to ’1’, this bit will flash status indicator LED 1. Bit 16 of the register will over-
ride this bit.
When set to ’1’, this bit will turn on status indicator LED 4.
When set to ’1’, this bit will turn on status indicator LED 3.
When set to ’1’, this bit will turn on status indicator LED 2.
When set to ’1’, this bit will turn on status indicator LED 1.
This bit controls a chip output pin to switch high or low and can be used to select differ-
ent PHY interfaces, etc. When this bit is off, or a logical ‘0’, the chip output is high, or a
logical ‘1’.
For debug reasons, the driven of the address for EPROM and PHY fetches can be
turned off with this bit.
When set to ’1’, this bit allow indicator LED 1 to reflect the status of Carrier Detect. This
is a chip input.
When set to ’1’, if a parity error occurs on the PHY Data bus during a PHY register
access, bit 1 of the NPBUS Status Register will be set.
When this bit is ’1’, the upper eight bits of a 16-bit PHY data (bits 15-8) bus will be
transferred over 47- 40 bits of the ENSTATE chip I/O bus.
When this bit is ’0’, the external PHY register space can be accessed through PHY 1
Registers or PHY 2 Registers. Also, the SONET Framer register space can be
accessed through the EPROM access registers, NPBUS EPROM Address/Command
Register and NPBUS EPROM Data Register. By providing the byte framer address
(see Sonet Framer Core (FRAMR Chiplet Address Mapping) on page 525) in the
NPBUS EPROM Address/Command Register, the byte data can be read or written
from the NPBUS EPROM Data Register. When this bit is set to ’1’, the internal SONET
framer registers can be accessed (see Sonet Framer Core (FRAMR Chiplet Address
Mapping) on page 525). The full offset range for this access is X'2100' to X'2FFF'.
When this bit is ’0’, PHY access speed is 200 ns (SUNI-like interface). When a ’1’,
access requires an acknowledge input response. This is to support a UTOPIA-like
micro-processor interface.
Allows bit 4 (Master enable) of the INTST Control Register to reset bit 4 of this register
(Disables Front End logic). This function assumes that bit 4 of the INTST Control Reg-
ister has already been enabled and that either a hardware or software event has
turned the bit off.
This bit will restart the external serial or parallel EPROM initialization code.
This bit powers up to a zero and keeps the internal SONET Framer in reset mode. Set-
ting this bit to a 1 will enable normal operation.
Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for
Description
IBM Processor for Network Resources
Register Initialization from EPROM Data
Page 429 of 676
IBM3206K0424