ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 403

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
PHY Level Interfaces
Entity 14: The PHY Interface (LINKC)
Functional Description
LINKC provides the interface between the IBM3206K0424 and either an ATM PHY device or, when the inter-
nal framer is selected, a serializer/deserializer device. LINKC is composed of three pieces. LINKX, which
contains all the registers described below, is clocked with the same clock as other parts of the chip. LINKT,
the transmit logic, is clocked on the transmit clock, which is selected via the Clock Control Register
(described in Clock Control Register (Nibble Aligned) on page 516). LINKR, the receive logic, is clocked on
the receive clock, which is also selectable via the Clock Control Register. Transmit and receive transfers are
synchronized via their respective interface transfer clock. The data path size is 8- or 16-bits wide and is
selectable through bit 3 of the control register. The PHY devices that the IBM3206K0424 interfaces to are:
New features added to LINKC are:
Multi-Drop
When the IBM3206K0424 is in multi-drop Utopia mode, it supports four external PHY devices. Each port is
associated with a configuration. Four configurations are provided so up to four different types of PHYs can be
connected to the IBM3206K0424. This allows the user to mix cell and POS-PHY devices on the transmit
and/or receive interface.
The multi drop PHY devices supported are Utopia Level 2 (cell based) and PMC Sierra POS-PHY
(packet/frame based). The IBM3206K0424 will select which PHY device will transfer data next by polling
each of the devices to determine which PHYs can transfer data. A round-robin switching scheme is used to
determine which PHY has the priority if more then one wants to transmit/receive data. The IBM3206K0424
will switch to a new drop when a cell has been received/transmitted (for a cell-based PHY) or when 64 bytes
or EOP has been received/transmitted (for POS-PHY PHYs). The transmit and receive sides of LINK are
separately configurable for multi-drop mode (bits 1 and 0 of the global control register).
POS-PHY
The POS-PHY interface complies with the PMC Sierra POS-PHY Level 2 Specification. The IBM3206K0424
polls each POS-PHY device to determine its status on both the receive and transmit side. It looks to switch to
a different port when 64 bytes or EOP (End of Packet) have been transferred between the POS-PHY and
itself. The IBM3206K0424 does not support direct status indication or byte-level transfers. Therefore, the
PHY must be programmed to always be able to send/receive at least 64 bytes of information. The RMOD
signal will only be looked at when REOP is b'1'; at all other times it will be ignored. POS-PHY devices should
be configured so that they will only signal they are ready for a transfer if they have 64 bytes free in their
receive buffer and 64 bytes or EOP in their transmit FIFO.
pnr25.chapt05.01
August 14, 2000
• PMC SIERRA PM5346 SUNI LITE FOR SONET STS-3c 155.52 MB/s
• UTOPIA 8 or 16 bit interface
• PMC SIERRA POS-PHY
• Multi-drop Utopia support
• PMC SIERRA POS-PHY interface support
IBM Processor for Network Resources
The PHY Interface (LINKC)
Page 403 of 676
IBM3206K0424