ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 377

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
RXQUE Structure
Each queue has a number of registers that define the queue and its behavior:
Lower bound
Properties
Head pointer
Tail pointer
Queue length
Threshold
Next lower bound
RXQUE Initialization
To set up a receive queue, at least two pieces of information are needed. The first is the receive queue’s set
of properties, and the second is its base address.
The following restrictions should be taken into account when setting up a queue:
pnr25.chapt05.01
August 14, 2000
• The properties register must be set up before the lower-bound and next-lower-bound registers can be set
• The lower bound and next lower bound must be at least 1K aligned. The low order 10 bits of these regis-
• The head and tail pointers are initialized when the lower bound register is written. These registers are
• The threshold is level sensitive, so as long as the queue length is greater than or equal to the threshold,
• All registers, except the threshold and next-lower-bound registers, can only be written in diagnostic mode
up.
ters are not writable, so the minimum physical size of a receive queue is 1024 bytes (256 32-bit entries).
The alignment should correspond to the size specified in the properties register.
only writable for diagnostic purposes.
the appropriate status bit is driven.
and are intended to only be written once when they are set up.
Pointer to starting address of queue's buffer
Indicates the queue's size, type, and behavior
Pointer to head of queue
Pointer to the next free entry in queue - points to head if queue is full or empty
Current length of the queue
Length threshold used to generate interrupts
Pointer to starting address of a system receive queue's next buffer
IBM Processor for Network Resources
Receive Queues (RXQUE)
Page 377 of 676
IBM3206K0424