ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 520

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Entity 21: JTAG Interface Logic (CJTAG)
The CJTAG entity contains logic to support a test access port (TAP) controller compliant with the IEEE
1149.1-1993 standard. The TAP controller is accessed via the following five pins:
TCK
TMS
TDI
TDO
TRST
The proper operation of these signals and the TAP controller is defined in the IEEE 1149.1-1993 standard.
Scanning
The TAP controller supports two types of scans: instruction scans and data scans. Instruction scans control
the type of operation and select which (if any) scan chains are involved in the operation. Data scans generally
clock the data on TDI into the selected scan chain.
JTAG Interface Logic (CJTAG)
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Test Clock. All activity of the JTAG interface is clocked via TCK. Events occur on
the rising or falling edge of TCK. TCK should have a maximum frequency of
20MHz.
Test Mode Select. Test Mode Select is used to control state transitions in the TAP
controller. These transitions occur on the rising edge of TCK. The BTR selected for
TMS should be one with an internal pullup.
Test Data In. Serial data input to the JTAG logic. The BTR selected for TDI should
be one with an internal pullup.
Test Data Out. Serial data output to the JTAG logic.
Test Reset. Asynchronous, minus active reset to the TAP controller. Assertion of
this input causes the TAP controller to reset and the JTAG instruction register to
load the IDCODE instruction. It is preferable to have TRST be independent of any
chip reset. With an independent reset, the JTAG logic can be reset, allowing the
chip’s state to be examined without having to reset the core logic. The BTR
selected for TRST should be one with an internal pullup.
pnr25.chapt05.01
August 14, 2000
Preliminary