ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 282

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Transmit Buffer (CSKED)
Page 282 of 676
Bit(s)
10-8
17
16
15
14
13
12
11
7
6
5
4
3
2
1
0
Use weighted fair queueing for low
priority
Reserved
Reserved
Queue the LCD address if freeing
and queueing
Disable virtual buffer error detec-
tion
Disable queuing virtual buffer
errors
Flush Transmit LCD Cache
SEGBF Queue Length Threshold
Disable SEGBF Queue Length in
Scheduling
Priority of buffer requests
Enable timers
Reschedule Packets in the Slow
Queue to the Fast Queue
Enable High Priority Traffic
Enable Medium Priority Traffic
Enable Low Priority Traffic
Enable Cell Scheduling
Name
Setting this bit will cause low priority traffic to be scheduled using weighted fair queue-
ing. The peak interval in the LCD is used to provide a relative weight in determining the
amount of bandwidth the connection will use. For example, a peak interval of one will
use twice the bandwidth as a connection with a peak interval of two. The average inter-
val specifies the maximum rate that the connection can use. For example if the aver-
age interval is set to two, the maximum rate at which it can send a cell is every two
timeslot times (as defined in the Timeslot Prescaler Register).
Reserved.
Reserved.
Setting this bit will cause the LCD address, instead of the packet address, to be
queued if both freeing and queueing on transmit are complete.
Setting this bit will cause the buffer enqueue logic to ignore virtual buffer errors.
If virtual buffer error detection is not disabled, detected errors will be queued. If this bit
is set, this queueing is disabled and the buffer will be freed.
If this bit is set, the transmit LCD cache will be flushed. This bit will be reset after the
cache has been flushed. Flushing the cache should not be needed in normal opera-
tion.
Cells can be queued in SEGBF up to the number specified in this register. The default
is seven, which is above the limit for pass two. Writing these bits to ’0’ will also disable
this function.
CSKED will normally include SEGBFs queue length in the calculations when resched-
uling a cell. If this bit is on it will disable this function and the cell will be scheduled as if
the cells were transferred when SEGBF accepted the cells.
If this bit is not set, scheduling requests have a higher priority than buffer requests. If
this bit is set this priority is reversed. It should be set if a significant percentage of pack-
ets are only a few cells in length.
Timer descriptors can be enqueued to this entity that will cause a DMA descriptor to be
executed on expiration. If these timers are used, this bit must be set. If they are not
used, this bit should be reset.
This function is not implemented in pass one. It is implemented in pass two.
If the average or peak interval is greater than 255, the cells will be scheduled in the
slow queue. The slow queues will be serviced every 64 pre-scaler time units. This
means that a jitter of up to 64 pre-scaler time units should be expected for slow traffic.
If this bit is set, packets in the slow queue will be rescheduled at the appropriate time to
the fast queue. This will decrease the variation in the scheduling but may cause some
performance degradation if traffic is heavy.
For each priority enabled 16KB of Control Memory must be reserved for timing data. If
only one or two priorities are to be used, bits corresponding to unused priorities should
be cleared to improve performance.
Enable Medium Priority Traffic.
Enable Low Priority Traffic.
If this bit is off, no primitives will be handled or cells scheduled.
Description
pnr25.chapt05.01
August 14, 2000
Preliminary